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Mobile Intel Pentium 4 Processor-M
Datasheet
June 2003
Order Number: 250686-007
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information contained herein supersedes previously published specifications on these devices from Intel. Actual system-level properties, such as skin temperature, are a function of various factors, including component placement, component power characteristics, system power and thermal management techniques, software application usage and general system design. Intel is not responsible for its customers' system designs, nor is Intel responsible for ensuring that its customers' products comply with all applicable laws and regulations. Intel provides this and other thermal design information for informational purposes only. System design is the sole responsibility of Intel's customers, and Intel's customers should not rely on any Intelprovided information as either an endorsement or recommendation of any particular system design characteristics. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Mobile Intel Pentium 4 Processor-M may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 or by visiting Intel's Website at http://www.intel.com Copyright (c) Intel Corporation 2000-2003. Intel, Pentium, Intel NetBurst, and SpeedStep are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States and other countries. * Other brands and names are the property of their respective owners.
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Mobile Intel Pentium 4 Processor-M Datasheet
Contents
1. Introduction......................................................................................................................... 9 1.1 1.2 2. 2.1 2.2 2.3 Terminology......................................................................................................... 11 References .......................................................................................................... 11 System Bus and GTLREF ................................................................................... 13 Power and Ground Pins ...................................................................................... 13 Decoupling Guidelines ........................................................................................ 13 2.3.1 VCC Decoupling ..................................................................................... 14 2.3.2 System Bus AGTL+ Decoupling............................................................. 14 2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking .......................14 Voltage Identification and Power Sequencing..................................................... 15 2.4.1 Enhanced Intel(R) SpeedStep(R) Technology............................................ 16 2.4.2 Phase Lock Loop (PLL) Power and Filter............................................... 17 2.4.3 Catastrophic Thermal Protection............................................................ 18 Signal Terminations, Unused Pins and TESTHI[10:0] ........................................ 18 System Bus Signal Groups ................................................................................. 20 Asynchronous GTL+ Signals............................................................................... 22 Test Access Port (TAP) Connection.................................................................... 22 System Bus Frequency Select Signals (BSEL[1:0])............................................ 22 Maximum Ratings................................................................................................ 23 Processor DC Specifications............................................................................... 23 AGTL+ System Bus Specifications ..................................................................... 34 System Bus AC Specifications ............................................................................ 35 Processor AC Timing Waveforms ....................................................................... 40 System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines ...........................................................................................................51 System Bus Signal Quality Specifications and Measurement Guidelines........... 52 System Bus Signal Quality Specifications and Measurement Guidelines........... 55 3.3.1 Overshoot/Undershoot Guidelines ......................................................... 55 3.3.2 Overshoot/Undershoot Magnitude ......................................................... 55 3.3.3 Overshoot/Undershoot Pulse Duration................................................... 55 3.3.4 Activity Factor......................................................................................... 56 3.3.5 Reading Overshoot/Undershoot Specification Tables............................ 56 3.3.6 Conformance Determination to Overshoot/Undershoot Specifications .. 57 Processor Pin-Out ............................................................................................... 64 Mobile Intel Pentium 4 Processor-M Pin Assignments........................................ 67 Alphabetical Signals Reference .......................................................................... 81 Thermal Specifications ........................................................................................ 90
Electrical Specifications.................................................................................................... 13
2.4
2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 3. 3.1 3.2 3.3
System Bus Signal Quality Specifications........................................................................ 51
4. 5.
Package Mechanical Specifications .................................................................................61 4.1 5.1 5.2 Pin Listing and Signal Definitions .....................................................................................67
6.
Thermal Specifications and Design Considerations......................................................... 89 6.1
Mobile Intel Pentium 4 Processor-M Datasheet
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Mobile Intel Pentium 4 Processor-M
6.1.1 6.1.2 7. 7.1 7.2
Thermal Diode........................................................................................ 90 Thermal Monitor ..................................................................................... 91
Configuration and Low Power Features........................................................................... 93 Power-On Configuration Options ........................................................................ 93 Clock Control and Low Power States.................................................................. 93 7.2.1 Normal State .......................................................................................... 93 7.2.2 AutoHALT Powerdown State ................................................................. 93 7.2.3 Stop-Grant State .................................................................................... 94 7.2.4 HALT/Grant Snoop State ....................................................................... 95 7.2.5 Sleep State............................................................................................. 95 7.2.6 Deep Sleep State ................................................................................... 95 7.2.7 Deeper Sleep State ................................................................................ 96 Enhanced Intel SpeedStep Technology .............................................................. 96 Logic Analyzer Interface (LAI) ............................................................................ 97 8.1.1 Mechanical Considerations .................................................................... 97 8.1.2 Electrical Considerations........................................................................ 97
7.3 8. 8.1
Debug Tools Specifications.............................................................................................. 97
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Mobile Intel Pentium 4 Processor-M Datasheet
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 VCCVID Pin Voltage and Current Requirements ................................................ 15 Typical VCCIOPLL, VCCA and VSSA Power Distribution .................................. 17 Phase Lock Loop (PLL) Filter Requirements ..................................................... 18 Illustration of VCC Static and Transient Tolerances (VID = 1.30 V).................... 26 Illustration of VCC Static and Transient Tolerances (VID = 1.20 V).................... 28 Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting = 1.30 V) ................................................................................................. 29 ITPCLKOUT[1:0] Output Buffer Diagram ............................................................ 34 AC Test Circuit .................................................................................................... 41 TCK Clock Waveform.......................................................................................... 41 Differential Clock Waveform................................................................................ 42 Differential Clock Crosspoint Specification.......................................................... 43 System Bus Common Clock Valid Delay Timings............................................... 43 System Bus Reset and Configuration Timings....................................................44 Source Synchronous 2X (Address) Timings ....................................................... 44 Source Synchronous 4X Timings ........................................................................ 45 Power Up Sequence ........................................................................................... 46 Power Down Sequence....................................................................................... 46 Test Reset Timings ............................................................................................. 47 THERMTRIP# to Vcc Timing............................................................................... 47 FERR#/PBE# Valid Delay Timing ....................................................................... 47 TAP Valid Delay Timing ...................................................................................... 48 ITPCLKOUT Valid Delay Timing ......................................................................... 48 Stop Grant/Sleep/Deep Sleep Timing .................................................................49 Enhanced Intel SpeedStep Technology/Deep Sleep Timing .............................. 50 BCLK Signal Integrity Waveform......................................................................... 52 Low-to-High System Bus Receiver Ringback Tolerance..................................... 53 High-to-Low System Bus Receiver Ringback Tolerance..................................... 53 Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers ................................................................................................................. 54 High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers ................................................................................................................. 54 Maximum Acceptable Overshoot/Undershoot Waveform ................................... 59 Micro-FCPGA Package Top and Bottom Isometric Views .................................. 61 Micro-FCPGA Package Top and Side View........................................................ 62 Micro-FCPGA Package - Bottom View................................................................ 64 The Coordinates of the Processor Pins as Viewed From the Top of the Package. ............................................................................................................. 65 Clock Control States............................................................................................ 94
Mobile Intel Pentium 4 Processor-M Datasheet
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Mobile Intel Pentium 4 Processor-M
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 References.......................................................................................................... 11 Core Frequency to System Bus Multipliers ......................................................... 14 Voltage Identification Definition........................................................................... 16 System Bus Pin Groups ...................................................................................... 21 BSEL[1:0] Frequency Table for BCLK[1:0] ......................................................... 22 Processor DC Absolute Maximum Ratings ......................................................... 23 Voltage and Current Specifications..................................................................... 24 IMVP-III Voltage Regulator Tolerances for VID = 1.30 V Operating Mode (Maximum Performance Mode)........................................................................... 25 IMVP-III Voltage Regulator Tolerances for VID = 1.20 V Operating Mode (Battery Optimized Mode) ................................................................................... 27 IMVP-III Deep Sleep State Voltage Regulator Tolerances for Maximum Performance Mode (VID = 1.30 V, VID Offset = 4.62%) ..................................... 28 IMVP-III Deep Sleep State Voltage Regulator Tolerances for Battery Optimized Mode (VID = 1.20 V, VID Offset = 4.62%) .......................................................... 29 System Bus Differential BCLK Specifications ..................................................... 30 AGTL+ Signal Group DC Specifications ............................................................. 31 Asynchronous GTL+ Signal Group DC Specifications ........................................ 32 PWRGOOD and TAP Signal Group DC Specifications ...................................... 33 ITPCLKOUT[1:0] DC Specifications.................................................................... 33 BSEL [1:0] and VID[4:0] DC Specifications......................................................... 34 AGTL+ Bus Voltage Definitions........................................................................... 35 System Bus Differential Clock Specifications...................................................... 36 System Bus Common Clock AC Specifications .................................................. 36 System Bus Source Synch AC Specifications AGTL+ Signal Group .................. 37 Miscellaneous Signals AC Specifications ........................................................... 38 System Bus AC Specifications (Reset Conditions) ............................................. 38 TAP Signals AC Specifications ........................................................................... 39 ITPCLKOUT[1:0] AC Specifications .................................................................... 39 Stop Grant/Sleep/Deep Sleep/Enhanced Intel SpeedStep Technology AC Specifications ...................................................................................................... 40 BCLK Signal Quality Specifications .................................................................... 51 Ringback Specifications for AGTL+ and Asynchronous GTL+ Signal Groups.... 52 Ringback Specifications for PWRGOOD Input and TAP Signal Groups............. 53 Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance ............................................................................................................ 57 Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance ............................................................................................................ 58 Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance ............................................................................................................ 58 Asynchronous GTL+, PWRGOOD Input, and TAP Signal Groups Overshoot/Undershoot Tolerance ....................................................................... 59 Micro-FCPGA Package Dimensions ................................................................... 63 Pin Listing by Pin Name ...................................................................................... 68 Pin Listing by Pin Number ................................................................................... 74 Signal Description ............................................................................................... 81 Power Specifications for the Mobile Intel Pentium 4 Processor-M...................... 89 Thermal Diode Interface...................................................................................... 90
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Mobile Intel Pentium 4 Processor-M Datasheet
40 41
Thermal Diode Specifications.............................................................................. 90 Power-On Configuration Option Pins .................................................................. 93
Mobile Intel Pentium 4 Processor-M Datasheet
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Mobile Intel Pentium 4 Processor-M
Revision History
Date March 2002 April 2002 Revision 001 002 Initial release of the Datasheet Updates include: * * * * * June 2002 003 Added new processor speeds: 1.4 GHz, 1.5 GHz, & 1.8 GHz Added PROCHOT# signal in Table 21 Updated signal description for PROCHOT# in Table 37 and Section 6.1.2 Updated the description of the Enhanced Intel Speedstep Technology in sections 2.4.1 and 7.3 Updated PWRGOOD signal in Table 3, Section 2.7, Table 14, Table 21, Table 28, Table 35, Figure 28, and FIgure 29 Added specifications for new processor speeds: 1.90 GHz and 2 GHz Added die length and die width for processors based on B0-step shrink process in Table 33 Added 2.2 GHz Mobile Intel Pentium 4 Processor-M specifications. Current and power specifications updated in Table 7 & Table 38. Corrected STPCLK#/SLP# timing relationship in Section 7.2.3 to match parameter T75. Added 2.4 GHz Mobile Intel Pentium 4 Processor-M specifications. Current and power specifications updated in Table 7 & Table 38. Clarified DBI[3:0]# and THERMTRIP# descriptions in Table 37. Clarified thermal solution requirements in Section 6. Added 2.5 GHz Mobile Intel Pentium 4 Processor-M specifications. Current and power specifications updated in Table 7 & Table 38. Added 2.6 GHz Mobile Intel Pentium 4 Processor-M specifications. Updated note 5 in Table 22. Updated THERMTRIP# description in Table 37. Description
Updates include: * *
September 2002
004
Updates include: * * *
January 2003
005
Updates include: * * * *
April 2003
006
Updates include: * *
June 2003
007
Updates include: * * *
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Mobile Intel Pentium 4 Processor-M Datasheet
Introduction
1.
Introduction
The Mobile Intel Pentium 4 Processor-M is the first Intel mobile processor with the Intel NetBurstTM micro-architecture. The Mobile Intel Pentium 4 Processor-M utilizes a 478-pin, Micro Flip-Chip Pin Grid Array (Micro-FCPGA) package, and plugs into a surface-mount, Zero Insertion Force (ZIF) socket. The Mobile Intel Pentium 4 Processor-M maintains full compatibility with IA32 software. In this document the Mobile Intel Pentium 4 Processor-M will be referred to as the "Mobile Intel Pentium 4 Processor-M" or simply "the processor." The Intel NetBurst micro-architecture features include hyper-pipelined technology, a rapid execution engine, a 400-MHz system bus, and an execution trace cache. The hyper pipelined technology doubles the pipeline depth in the Mobile Intel Pentium 4 Processor-M allowing the processor to reach much higher core frequencies. The rapid execution engine allows the two integer ALUs in the processor to run at twice the core frequency, which allows many integer instructions to execute in 1/2 clock tick. The 400-MHz system bus is a quad-pumped bus running off a 100-MHz system clock making 3.2 GB/sec data transfer rates possible. The execution trace cache is a first level cache that stores approximately 12-k decoded micro-operations, which removes the instruction decoding logic from the main execution path, thereby increasing performance. Additional features within the Intel NetBurst micro-architecture include advanced dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2). The advanced dynamic execution improves speculative execution and branch prediction internal to the processor. The advanced transfer cache is a 512 kB, on-die level 2 (L2) cache. A new floating point and multi media unit has been implemented which provides superior performance for multi-media and mathematically intensive applications. Finally, SSE2 adds 144 new instructions for double-precision floating point, SIMD integer, and memory management. Power management capabilities such as AutoHALT, Stop-Grant, Sleep, Deep Sleep, and Deeper Sleep have been incorporated. The processor includes an address bus powerdown capability which removes power from the address and data pins when the system bus is not in use. This feature is always enabled on the processor. The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition. The new packed double-precision floating-point instructions enhance performance for applications that require greater range and precision, including scientific and engineering applications and advanced 3-D geometry techniques, such as ray tracing. The Mobile Intel Pentium 4 Processor-M's 400-MHz Intel NetBurst micro-architecture system bus utilizes a split-transaction, deferred reply protocol like the Intel Pentium 4 Processor. This system bus is not compatible with the P6 processor family bus. The 400-MHz Intel NetBurst microarchitecture system bus uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "double-clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3.2 Gbytes/second. The processor, when used in conjunction with the requisite Intel SpeedStep technology applet or its equivalent, supports Enhanced Intel SpeedStep technology, which enables real-time dynamic switching of the voltage and frequency between two performance modes. This occurs by switching the bus ratios, core operating voltage, and core processor speeds without resetting the system.
Mobile Intel Pentium 4 Processor-M Datasheet
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Introduction
The processor system bus uses a variant of GTL+ signalling technology called Assisted Gunning Transceiver Logic (AGTL+) signal technology. The Mobile Intel Pentium 4 Processor-M is available at the following core frequencies:
* 2.6 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in
Battery Optimized Mode at 1.20 V)
* 2.5 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in
Battery Optimized Mode at 1.20 V)
* 2.4 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in
Battery Optimized Mode at 1.20 V)
* 2.2 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in
Battery Optimized Mode at 1.20 V)
* 2.0 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in
Battery Optimized Mode at 1.20 V)
* 1.9 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in
Battery Optimized Mode at 1.20 V)
* 1.8 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in
Battery Optimized Mode at 1.20 V)
* 1.7 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in
Battery Optimized Mode at 1.20 V)
* 1.6 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in
Battery Optimized Mode at 1.20 V)
* 1.5 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in
Battery Optimized Mode at 1.20 V)
* 1.4 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in
Battery Optimized Mode at 1.20 V)
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Mobile Intel Pentium 4 Processor-M Datasheet
Introduction
1.1
Terminology
A "#" symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the "#" symbol implies that the signal is inverted. For example, D[3:0] = "HLHL" refers to a hex `A', and D[3:0]# = "LHLH" also refers to a hex "A" (H= High logic level, L= Low logic level). "System Bus" refers to the interface between the processor and system core logic (a.k.a. the chipset components). The system bus is a multiprocessing interface to processors, memory, and I/O. Commonly used terms are explained here for clarification:
* Processor -- For this document, the term processor shall mean the Mobile Intel Pentium 4
Processor-M in the 478-pin package.
* Keep out zone -- The area on or near the processor that system design can not utilize. * Intel 845MP/845MZ chipsets -- Mobile chipsets that will support the Mobile Intel
Pentium 4 Processor-M.
* Processor core -- Mobile Intel Pentium 4 Processor-M core die with integrated L2 cache. * Micro-FCPGA package -- Micro Flip-Chip Pin Grid Array package with 50-mil pin pitch.
1.2
References
Material and concepts available in the following documents may be beneficial when reading this document.
Table 1.
References
Document Mobile Intel Pentium Platform Design Guide 4 Processor-M and Intel 845MP/845MZ Chipset Order Number 250688-002
Intel Architecture Software Developer's Manual Volume I: Basic Architecture Volume II: Instruction Set Reference Volume III: System Programming Guide 245470 245471 245472
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Introduction
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Mobile Intel Pentium 4 Processor-M Datasheet
Electrical Specifications
2.
2.1
Electrical Specifications
System Bus and GTLREF
Most Mobile Intel Pentium 4 Processor-M system bus signals use Assisted Gunning Transceiver Logic (AGTL+) signalling technology. As with the Intel P6 family of microprocessors, this signalling technology provides improved noise margins and reduced ringing through low-voltage swings and controlled edge rates. The termination voltage level for the Mobile Intel Pentium 4 Processor-M AGTL+ signals is VCC, which is the operating voltage of the processor core. Previous generations of Intel mobile processors utilize a fixed termination voltage known as VCCT. The use of a termination voltage that is determined by the processor core allows better voltage scaling on the system bus for Mobile Intel Pentium 4 Processor-M. Because of the speed improvements to data and address bus, signal integrity and platform design methods have become more critical than with previous processor families. Design guidelines for the Mobile Intel Pentium 4 Processor-M system bus will be detailed in the Mobile Intel Pentium 4 Processor-M and Intel 845MP/ 845MZ Chipset Platform Design Guide. The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board. Termination resistors are provided on the processor silicon and are terminated to its core voltage (VCC). Intel's 845MP/845MZ chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the system board for most AGTL+ signals. However, some AGTL+ signals do not include on-die termination and must be terminated on the system board. For more information, refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide. The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the system bus, including trace lengths, is highly recommended when designing a system.
2.2
Power and Ground Pins
For clean on-chip power distribution, the Mobile Intel Pentium 4 Processor-M have 85 VCC (power) and 181 VSS (ground) inputs. All power pins must be connected to VCC, while all VSS pins must be connected to a system ground plane.The processor VCC pins must be supplied with the voltage determined by the VID (Voltage ID) pins and the loadline specifications (see Figure 4 to Figure 6).
2.3
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 7. Failure to do so can result in timing violations and/or
Mobile Intel Pentium 4 Processor-M Datasheet
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Electrical Specifications
affect the long term reliability of the processor. For further information and design guidelines, refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide.
2.3.1
VCC Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low-power states, must be provided by the voltage regulator solution. For more details on decoupling recommendations, please refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide.
2.3.2
System Bus AGTL+ Decoupling
The Mobile Intel Pentium 4 Processor-M integrates signal termination on the die and incorporates high frequency decoupling capacitance on the processor package. Decoupling must also be provided by the system motherboard for proper AGTL+ bus operation. For more information, refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide.
2.3.3
System Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the system bus interface speed as well as the core frequency of the processor. As in previous generation processors, the Mobile Intel Pentium 4 Processor-M core frequency is a multiple of the BCLK[1:0] frequency. Refer to Table 2 for the Mobile Intel Pentium 4 Processor-M supported ratios.
Table 2.
Core Frequency to System Bus Multipliers
Core Frequency 800 MHz 1.2 GHz 1.4 GHz 1.5 GHz 1.6 GHz 1.7 GHz 1.8 GHz 1.9 GHz 2.0 GHz 2.2 GHz 2.4 GHz 2.5 GHz 2.6 GHz NOTES: 1. Ratio is used for debug purposes only. Multiplication of System Core Frequency to System Bus Frequency 1/8 1/12 1/14 1/15 1/16 1/17 1/18 1/19 1/20 1/22 1/24 1/25 1/26 Notes2 1
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Mobile Intel Pentium 4 Processor-M Datasheet
Electrical Specifications
2. Listed frequencies are not necessarily committed production frequencies.
The Mobile Intel Pentium 4 Processor-M uses a differential clocking implementation. For more information on Mobile Intel Pentium 4 Processor-M clocking.
2.4
Voltage Identification and Power Sequencing
The voltage set by the VID pins is the nominal/typical voltage setting for the processor. A minimum voltage is provided in Table 7 and changes with frequency. This allows processors running at a higher frequency to have a relaxed minimum voltage specification. The specifications have been set such that one voltage regulator can work with all supported frequencies. The Mobile Intel Pentium 4 Processor-M uses five voltage identification pins, VID[4:0], to support automatic selection of power supply voltages. The VID pins for the Mobile Intel Pentium 4 Processor-M are open drain outputs driven by the processor VID circuitry. Table 3 specifies the voltage level corresponding to the state of VID[4:0]. A "1" in this table refers to a high-voltage level and a "0" refers to low-voltage level. Power source characteristics must be stable whenever the supply to the voltage regulator is stable. Refer to the Figure 16 for timing details of the power up sequence. Also refer to Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for implementation details. Mobile Intel Pentium 4 Processor-M's Voltage Identification circuit requires an independent 1.2-V supply. This voltage must be routed to the processor VCCVID pin. Figure 1 shows the voltage and current requirements of the VCCVID pin.
Figure 1. VCCVID Pin Voltage and Current Requirements
1.2V+10%
1.2V-5% 1V 150mA to 300mA
80mA
30mA 1mA 70nS 5nS
Mobile Intel Pentium 4 Processor-M Datasheet
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Electrical Specifications
Table 3.
Voltage Identification Definition
Processor Pins VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0.600 0.625 0.650 0.675 0.700 0.725 0.750 0.775 0.800 0.825 0.850 0.875 0.900 0.925 0.950 0.975 1.000 1.050 1.100 1.150 1.200 1.250 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 VCC_
2.4.1
Enhanced Intel(R) SpeedStep(R) Technology
The Mobile Intel Pentium 4 Processor-M, when used in conjunction with the requisite Intel SpeedStep technology applet or its equivalent, supports Enhanced Intel SpeedStep technology. Enhanced Intel SpeedStep technology allows the processor to switch between two core frequencies automatically based on CPU demand, without having to reset the processor or change the system bus frequency. The processor operates in two modes, the Maximum Performance mode or the Battery Optimized mode. Each frequency and voltage pair identifies the operating mode. The processor drives the VID[4:0] pins with the correct VID for the current operating mode. After reset, the processor will start in Battery Optimized mode. Any RESET# assertion will force the Mobile Intel Pentium 4 Processor-M Datasheet
16
Electrical Specifications
processor to the Battery Optimized mode. INIT# assertions ("soft" resets) and APIC bus INIT messages do not change the operating mode of the processor. Some electrical and thermal specifications are for a specific voltage and frequency. The Mobile Intel Pentium 4 Processor-M featuring Enhanced Intel SpeedStep technology will meet the electrical and thermal specifications specific to the current operating mode, and it is not guaranteed to meet the electrical and thermal specifications specific to the opposite operating mode. The timing specifications must be met when performing an operating mode transition.
2.4.2
Phase Lock Loop (PLL) Power and Filter
VCCA and VCCIOPLL are power sources required by the PLL clock generators on the Mobile Intel Pentium 4 Processor-M silicon. Since these PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e. maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VCCVID. A typical filter topology is shown in Figure 2. The AC low-pass requirements, with input at VCCVID and output measured across the capacitor (CA or CIO in Figure 2), is as follows:
* * * *
< 0.2 dB gain in pass band < 0.5 dB attenuation in pass band < 1 Hz > 34 dB attenuation from 1 MHz to 66 MHz > 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in Figure 3. For recommendations on implementing the filter refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide. Figure 2. Typical VCCIOPLL, VCCA and VSSA Power Distribution
V CCVID
L VCCA CA PLL Processor Core
VSSA CIO VCCIOPLL L
Mobile Intel Pentium 4 Processor-M Datasheet
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Electrical Specifications
.
Figure 3. Phase Lock Loop (PLL) Filter Requirements
0.2 dB 0 dB -0.5 dB forbidden zone
-28 dB
forbidden zone
-34 dB
DC passband
1 Hz
fpeak
1 MHz
66 MHz
fcore
high frequency band
NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz.
2.4.3
Catastrophic Thermal Protection
The Mobile Intel Pentium 4 Processor-M supports the THERMTRIP# signal for catastrophic thermal protection. Alternatively an external thermal sensor can be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. If the external thermal sensor detects a catastrophic processor temperature of 135C (maximum), or if the THERMTRIP# signal is asserted, the VCC supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor. Refer to Section 5.2 for more details on THERMTRIP#.
2.5
Signal Terminations, Unused Pins and TESTHI[10:0]
All NC pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future Mobile Intel Pentium 4 Processor-M. See Section 5.2 for a pin listing of the processor and the location of all NC pins.
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For reliable operation, always connect unused inputs or bidirectional signals that are not terminated on the die to an appropriate signal level. Note that on-die termination has been included on the Mobile Intel Pentium 4 Processor-M to allow signals to be terminated within the processor silicon. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon. Table 4 lists details on AGTL+ signals that do not include on-die termination. Unused active high inputs should be connected through a resistor to ground (VSS). Refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for the appropriate resistor values. Unused outputs can be left unconnected, however, this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. For unused AGTL+ input or I/O signals that don't have on-die termination, use pull-up resistors of the same value in place of the on-die termination resistors (RTT). See Table 18. The TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die termination. Inputs and used outputs must be terminated on the system board. Unused outputs may be terminated on the system board or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. Signal termination for these signal types is discussed in the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide. The TESTHI pins should be tied to the processor VCC using a matched resistor, where a matched resistor has a resistance value within + 20% of the impedance of the board transmission line traces. For example, if the trace impedance is 50 , then a value between 40 and 60 is required. The TESTHI pins may use individual pull-up resistors or be grouped together as detailed below. A matched resistor should be used for each group: 1. TESTHI[1:0] 2. TESTHI[5:2] 3. TESTHI[10:8] Additionally, if the ITPCLKOUT[1:0] pins are not used then they may be connected individually to VCC using matched resistors or grouped with TESTHI[5:2] with a single matched resistor. If they are being used, individual termination with 1-k resistors is required. Tying ITPCLKOUT[1:0] directly to VCC or sharing a pull-up resistor to VCC will prevent use of debug interposers. This implementation is strongly discouraged for system boards that do not implement an onboard debug port. As an alternative, group 2 (TESTHI[5:2]), and the ITPCLKOUT[1:0] pins may be tied directly to the processor VCC. This has no impact on system functionality. TESTHI[0] may also be tied directly to processor VCC if resistor termination is a problem, but matched resistor termination is recommended. In the case of the ITPCLKOUT[1:0] pins, direct tie to VCC is strongly discouraged for system boards that do not implement an onboard debug port. Tying any of the TESTHI pins together will prevent the ability to perform boundary scan testing. Pullup/down resistor requirements for the VID[4:0] and BSEL[1:0] signals are included in the signal descriptions in Section 5.
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Electrical Specifications
2.6
System Bus Signal Groups
In order to simplify the following discussion, the system bus signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependant upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 4 identifies which signals are common clock, source synchronous, and asynchronous.
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Table 4.
System Bus Pin Groups
Signal Group AGTL+ Common Clock Input Type Common clock Synchronous Signals1 BPRI#, DEFER#, RESET#2, RS[2:0]#, RSP#, TRDY# AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#2, BR0#2, DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR#
AGTL+ Common Clock I/O
Signals REQ[4:0]#, A[16:3]# AGTL+ Source Synchronous I/O Source Synchronous A[35:17]#
5 5
Associated Strobe ADSTB0# ADSTB1# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3#
D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3#
AGTL+ Strobes Asynchronous GTL+ Input4,5 Asynchronous GTL+ Output4 TAP Input4 TAP Output4 System Bus Clock
Common Clock Asynchronous Asynchronous Synchronous to TCK Synchronous to TCK N/A
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#, DPSLP#, GHI#, IGNNE#, INIT#5, LINT0/INTR, LINT1/NMI, SMI#5, SLP#, STPCLK# FERR#/PBE#, IERR#2, THERMTRIP#, PROCHOT# TCK, TDI, TMS, TRST# TDO BCLK[1:0], ITP_CLK[1:0]3 VCC, VCCA, VCCIOPLL, VCCVID, VID[4:0], VSS, VSSA, GTLREF[3:0], COMP[1:0], NC, TESTHI[5:0], TESTHI[10:8], ITPCLKOUT[1:0], PWRGOOD, THERMDA, THERMDC, SKTOCC#, VCC_SENSE, VSS_SENSE, BSEL[1:0], DBR#3
Power/Other
N/A
NOTES: 1. Refer to Section 5.2 for signal descriptions. 2. These AGTL+ signals do not have on-die termination. Refer to Section 2.5 for termination requirements. 3. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects. 4. These signal groups are not terminated by the processor. Signals not driven by the ICH3-M component must be terminated on the system board. Refer to Section 2.5 and the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for termination requirements and further details. 5. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 7.1 for details.
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Electrical Specifications
2.7
Asynchronous GTL+ Signals
Mobile Intel Pentium 4 Processor-M does not utilize CMOS voltage levels on any signals that connect to the processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# use GTL+ input buffers. Legacy output FERR#/PBE# and other non-AGTL+ signals (THERMTRIP# and PROCHOT#) use GTL+ output buffers. All of these signals follow the same DC requirements as AGTL+ signals, however the outputs are not actively driven high (during a logical 0 to 1 transition) by the processor (the major difference between GTL+ and AGTL+). These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the Asynchronous GTL+ signals are required to be asserted for at least two BCLKs in order for the processor to recognize them. See Section 2.11 and Section 2.13 for the DC and AC specifications for the Asynchronous GTL+ signal groups.
2.8
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the Mobile Intel Pentium 4 Processor-M be first in the TAP chain and followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage level. Similar considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may be required, with each driving a different voltage level.
2.9
System Bus Frequency Select Signals (BSEL[1:0])
The BSEL[1:0] are output signals used to select the frequency of the processor input clock (BCLK[1:0]). Table 5 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency. The Mobile Intel Pentium 4 Processor-M currently operates at a 400-MHz system bus frequency (selected by a 100-MHz BCLK[1:0] frequency). Individual processors will only operate at their specified system bus frequency. For more information about these pins refer to Section 5.2 and the appropriate platform design guidelines.
Table 5.
BSEL[1:0] Frequency Table for BCLK[1:0]
BSEL1 L L H H BSEL0 L H L H Function 100 MHz RESERVED RESERVED RESERVED
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2.10
Maximum Ratings
Table 6 lists the processor's maximum environmental stress ratings. The processor should not receive a clock while subjected to these conditions. Functional operating parameters are listed in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the processor contains protective circuitry to resist damage from Electro Static Discharge (ESD), one should always take precautions to avoid high static voltages or electric fields.
Table 6.
Processor DC Absolute Maximum Ratings
Symbol TSTORAGE VCC VinAGTL+ VinAsynch_GTL+ IVID Parameter Processor storage temperature Any processor supply voltage with respect to VSS AGTL+ buffer DC input voltage with respect to VSS Asynch GTL+ buffer DC input voltage with respect to VSS Max VID pin current Min -40 -0.3 -0.1 Max 85 1.75 1.75 Unit C V V Notes 2 1
-0.1
1.75 5
V mA
NOTES: 1. This rating applies to any processor pin. 2. Contact Intel for storage requirements in excess of one year.
2.11
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Section 5 for the pin signal definitions and signal pin assignments. Most of the signals on the processor system bus are in the AGTL+ signal group. The DC specifications for these signals are listed in Table 13. Previously, legacy signals and Test Access Port (TAP) signals to the processor used low-voltage CMOS buffer types. However, these interfaces now follow DC specifications similar to GTL+. The DC specifications for these signal groups are listed in Table 14 and Table 15. Table 7 through Table 17 list the DC specifications for the Mobile Intel Pentium 4 Processor-M and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. Unless specified otherwise, all specifications for the Mobile Intel Pentium 4 Processor-M are at TJ = 100C. Care should be taken to read all notes associated with each parameter.
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Electrical Specifications
Table 7.
Voltage and Current Specifications
Symbol VCC Parameter VCC for core logic Maximum Performance Mode Battery Optimized Mode VID supply voltage Transient Deeper Sleep voltage Static Deeper Sleep voltage Current for VCC at core frequency 2.60 GHz & 1.3 V 2.50 GHz & 1.3 V 2.40 GHz & 1.3 V 2.20 GHz & 1.3 V 2.00 GHz & 1.3 V 1.90 GHz & 1.3 V 1.80 GHz & 1.3 V 1.70 GHz & 1.3 V 1.60 GHz & 1.3 V 1.50 GHz & 1.3 V 1.40 GHz & 1.3 V 1.20 GHz & 1.2 V Current for VID supply ICC Stop-Grant and ICCSleep at 1.3 V (for > 2.0 GHz) 1.3 V (for <= 2.0 GHz) 1.2 V ICC Deep Sleep at IDSLP IDPRSLP ITCC ICC PLL 1.3 V 1.2 V ICC Deeper Sleep at 1.0V ICC TCC active ICC for PLL pins 9.0 8.3 6.9 ICC 60 A A A mA 8 10 9 38.8 37.7 36.7 34.5 33.3 32.2 31.0 29.9 28.7 27.5 26.3 22.1 300 10.5 10.1 8.9 -5% 0.91 0.95 Min Typ 1.3 1.2 1.2 1.00 1.00 +10% 1.09 1.05 Max Unit V V V V Notes1 2, 3, 4, 5, 7, 8,11 2, 12 2 2
VCCVID
VCCDPRSLP VCCDPRSLP,DC
ICC
A
4, 5, 8, 9
IVCCVID ISGNT, ISLP
mA
A
6, 9
NOTES: 1. Unless otherwise noted, all specifications in this table are based on latest post-silicon measurements available at the time of publication. 2. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.4 and Table 3 for more information. The VID bits will set the typical VCC with the minimum being defined according to current consumption at that voltage. 3. The voltage specification requirements are measured at the system board socket ball with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 4. Refer to Table 8 to Table 11 and Figure 4 to Figure 6 for the minimum, typical, and maximum VCC (measured at the system board socket ball) allowed for a given current. The processor should not be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current. Failure to adhere to this specification can affect the long term reliability of the processor. 5. VCC_MIN is defined at ICC_MAX. 6. The current specified is also for AutoHALT State. 7. Typical VCC indicates the VID encoded voltage. Voltage supplied must conform to the load line specification shown in Table 8 to Table 11. 8. The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT# is the same as the maximum ICC for the processor. 9. Maximum specifications for ICC Core, ICC Stop-Grant, ICC Sleep, and ICC Deep Sleep are specified at VCC Static Max. derived from the tolerances in Table 8 through Table 11, TJ Max., and under maximum signal loading conditions.
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Mobile Intel Pentium 4 Processor-M Datasheet
Electrical Specifications
10.The specification is defined per PLL pin. 11.The voltage response to a processor current load step (transient) must stay within the Transient Voltage Tolerance Window. The voltage surge or droop response measured in this window is typically on the order of several hundred nanoseconds to several microseconds. The Transient Voltage Tolerance Window is defined as follows: Case a) Load Current Step Up: e.g., from Icc = I_leakage to Icc = Icc_max. Allowable Vcc_min is defined as minimum transient voltage at Icc = Icc_max for a period of time lasting several hundred nanoseconds to several microseconds after the transient event. Case b) Load Current Step Down: e.g., form Icc = Icc_max to Icc = I_leakage. Allowable Vcc_max is defined as the maximum transient voltage at Icc = I_leakage for a period of time lasting several hundred nanoseconds to several microseconds after the transient event. 12.This specification applies to both static and transient components. The rising edge of VCCVID must be monotonic from 0 to 1.1 V. See Figure 1 for current requirements. In this case, monotonic is defined as continuously increasing with less than 50 mV of peak to peak noise for any width greater than 2 nS superimposed on the rising edge.
Table 8.
IMVP-III Voltage Regulator Tolerances for VID = 1.30 V Operating Mode (Maximum Performance Mode)
ICC (A) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 21.0 22.0 23.0 24.0 VCC Nominal (V) 1.300 1.298 1.296 1.294 1.292 1.290 1.288 1.286 1.284 1.282 1.280 1.278 1.276 1.274 1.272 1.270 1.268 1.266 1.264 1.262 1.260 1.258 1.256 1.254 1.252 VCC Static Min (V) 1.275 1.273 1.271 1.269 1.267 1.265 1.263 1.261 1.259 1.257 1.255 1.253 1.251 1.249 1.247 1.245 1.243 1.241 1.239 1.237 1.235 1.233 1.231 1.229 1.227 VCC Static Max (V) 1.325 1.323 1.321 1.319 1.317 1.315 1.313 1.311 1.309 1.307 1.305 1.303 1.301 1.299 1.297 1.295 1.293 1.291 1.289 1.287 1.285 1.283 1.281 1.279 1.277 VCC Transient Min (V) 1.255 1.253 1.251 1.249 1.247 1.245 1.243 1.241 1.239 1.237 1.235 1.233 1.231 1.229 1.227 1.225 1.223 1.221 1.219 1.217 1.215 1.213 1.211 1.209 1.207 VCC Transient Max (V) 1.345 1.343 1.341 1.339 1.337 1.335 1.333 1.331 1.329 1.327 1.325 1.323 1.321 1.319 1.317 1.315 1.313 1.311 1.309 1.307 1.305 1.303 1.301 1.299 1.297
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Electrical Specifications
Table 8.
IMVP-III Voltage Regulator Tolerances for VID = 1.30 V Operating Mode (Maximum Performance Mode)
ICC (A) 25.0 26.0 27.0 28.0 29.0 30.0 31.0 32.0 33.0 34.0 35.0 36.0 37.0 38.0 39.0 40.0 VCC Nominal (V) 1.250 1.248 1.246 1.244 1.242 1.240 1.238 1.236 1.234 1.232 1.230 1.228 1.226 1.224 1.222 1.220 VCC Static Min (V) 1.225 1.223 1.221 1.219 1.217 1.215 1.213 1.211 1.209 1.207 1.205 1.203 1.201 1.199 1.197 1.195 VCC Static Max (V) 1.275 1.273 1.271 1.269 1.267 1.265 1.263 1.261 1.259 1.257 1.255 1.253 1.251 1.249 1.247 1.245 VCC Transient Min (V) 1.205 1.203 1.201 1.199 1.197 1.195 1.193 1.191 1.189 1.187 1.185 1.183 1.181 1.179 1.177 1.175 VCC Transient Max (V) 1.295 1.293 1.291 1.289 1.287 1.285 1.283 1.281 1.279 1.277 1.275 1.273 1.271 1.269 1.267 1.265
Figure 4. Illustration of VCC Static and Transient Tolerances (VID = 1.30 V)
Mobile Northwood Load Line for VID = 1.30V
1.400
Vcc Transient Maximum 1.350 Vcc Static Maximum Vcc Nominal 1.300
1.250 VCC 1.200 Vcc Static Minimum 1.150 Vcc Transient 1.100 1.050
.0 .0 8. 0 .0 .0 .0 .0 .0 .0 .0 .0 .0 .0 38 .0 4. 0 6. 0 0. 0 2. 0 20 16 18 22 12 14 24 34 36 26 28 40 10 30 32 .0 .0 .0
Icc Maximum
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Table 9.
IMVP-III Voltage Regulator Tolerances for VID = 1.20 V Operating Mode (Battery Optimized Mode)
ICC (A) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 21.0 22.0 23.0 24.0 25.0 VCC Nominal (V) 1.176 1.174 1.172 1.170 1.168 1.166 1.164 1.162 1.160 1.158 1.156 1.154 1.152 1.150 1.148 1.146 1.144 1.142 1.140 1.138 1.136 1.134 1.132 1.130 1.128 1.126 VCC Static Min (V) 1.151 1.149 1.147 1.145 1.143 1.141 1.139 1.137 1.135 1.133 1.131 1.129 1.127 1.125 1.123 1.121 1.119 1.117 1.115 1.113 1.111 1.109 1.107 1.105 1.103 1.101 VCC Static Max (V) 1.201 1.199 1.197 1.195 1.193 1.191 1.189 1.187 1.185 1.183 1.181 1.179 1.177 1.175 1.173 1.171 1.169 1.167 1.165 1.163 1.161 1.159 1.157 1.155 1.153 1.151 VCC Transient Min (V) 1.131 1.129 1.127 1.125 1.123 1.121 1.119 1.117 1.115 1.113 1.111 1.109 1.107 1.105 1.103 1.101 1.099 1.097 1.095 1.093 1.091 1.089 1.087 1.085 1.083 1.081 VCC Transient Max (V) 1.221 1.219 1.217 1.215 1.213 1.211 1.209 1.207 1.205 1.203 1.201 1.199 1.197 1.195 1.193 1.191 1.189 1.187 1.185 1.183 1.181 1.179 1.177 1.175 1.173 1.171
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Electrical Specifications
Figure 5. Illustration of VCC Static and Transient Tolerances (VID = 1.20 V)
Mobile Northwood Load Line for VID = 1.20V
1.250
Vcc Transient Maximum Vcc Static Maximum 1.200 Vcc Nominal
1.150 VCC 1.100
Vcc Static Minimum 1.050 Vcc Transient Minimum
1.000
0. 0 1. 0 2. 0 3. 0 4. 0 5. 0 6. 0 7. 0 8. 0 9. 0 10 .0 11 .0 12 .0 13 .0 14 .0 15 .0 16 .0 17 .0 18 .0 19 .0 20 .0 21 .0 22 .0 23 .0 24 .0 25 .0
ICC Maximum
Table 10. IMVP-III Deep Sleep State Voltage Regulator Tolerances for Maximum Performance Mode (VID = 1.30 V, VID Offset = 4.62%)
ICC (A) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 VCC Nominal (V) 1.240 1.238 1.236 1.234 1.232 1.230 1.228 1.226 1.224 1.222 1.220 VCC Static Min (V) 1.215 1.213 1.211 1.209 1.207 1.205 1.203 1.201 1.199 1.197 1.195 VCC Static Max (V) 1.265 1.263 1.261 1.259 1.257 1.255 1.253 1.251 1.249 1.247 1.245 VCC Transient Min (V) 1.195 1.193 1.191 1.189 1.187 1.185 1.183 1.181 1.179 1.177 1.175 VCC Transient Max (V) 1.285 1.283 1.281 1.279 1.277 1.275 1.273 1.271 1.269 1.267 1.265
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Table 11. IMVP-III Deep Sleep State Voltage Regulator Tolerances for Battery Optimized Mode (VID = 1.20 V, VID Offset = 4.62%)
ICC (A) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VCC Nominal (V) 1.145 1.143 1.141 1.139 1.137 1.135 1.133 1.131 1.129 VCC Static Min (V) 1.120 1.118 1.116 1.114 1.112 1.110 1.108 1.106 1.104 VCC Static Max (V) 1.170 1.168 1.166 1.164 1.162 1.160 1.158 1.156 1.154 VCC Transient Min (V) 1.100 1.098 1.096 1.094 1.092 1.090 1.088 1.086 1.084 VCC Transient Max (V) 1.190 1.188 1.186 1.184 1.182 1.180 1.178 1.176 1.174
Figure 6. Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting = 1.30 V)
Northwood Deep Sleep Load Line for VID = 1.30V
1.300 Transient Maximum 1.280 Static Maximum 1.260 Vcc Nominal
1.240
1.220 VCC 1.200 Static Minimum 1.180
1.160
Transient Minimum
1.140
1.120 0 1 2 3 4 5 Isb Maximum 6 7 8 9 10
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Electrical Specifications
Table 12. System Bus Differential BCLK Specifications
Symbol VL VH VCROSS(abs) VCROSS(rel) VCROSS VOV VUS VRBM VTM Parameter Input Low Voltage Input High Voltage Absolute Crossing Point Relative Crossing Point Range of Crossing Points Overshoot Undershoot Ringback Margin Threshold Margin Min -0.150 0.660 0.250 0.250 + 0.5(VHavg - 0.710) N/A N/A -0.300 0.200 VCROSS - 0.100 Typ 0.000 0.710 N/A N/A N/A N/A N/A N/A N/A Max N/A 0.850 0.550 0.550 + 0.5(VHavg - 0.710) 0.140 VH + 0.3 N/A N/A VCROSS + 0.100 Unit V V V V V V V V V Figure 10 10 10, 11 10, 11 10, 11 10 10 10 10 2,3,8 2,3,8,9 2,10 4 5 6 7 Notes1
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1. 3. VHavg is the statistical average of the VH measured by the oscilloscope. 4. Overshoot is defined as the absolute value of the maximum voltage. 5. Undershoot is defined as the absolute value of the minimum voltage. 6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback. 7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis. 8. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 9. VHavg can be measured directly using "Vtop" on Agilent* scopes and "High" on Tektronix* scopes. 10.VCROSS is defined as the total variation of all crossing voltages as defined in note 2.
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Table 13. AGTL+ Signal Group DC Specifications
Symbol GTLREF VIH VIL VOH IOL IHI ILO RON Parameter Reference Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Current Pin Leakage High Pin Leakage Low Buffer On Resistance Min 2/3 Vcc - 2% 1.10*GTLREF 0.0 N/A N/A N/A N/A 7 Max 2/3 Vcc + 2% VCC 0.9*GTLREF Vcc 50 100 500 11 Unit V V V V mA A A 2,6 3,4,6 7 6 8 9 5 Notes1
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality specifications in Section 3. 5. Refer to processor I/O Buffer Models for I/V characteristics. 6. The VCC referred to in these specifications is the instantaneous VCC. 7. Vol max of 0.450 Volts is guaranteed when driving into a test load of 50 as indicated in Figure 8. 8. Leakage to VSS with pin held at VCC. 9. Leakage to VCC with pin held at 300 mV.
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Electrical Specifications
Table 14. Asynchronous GTL+ Signal Group DC Specifications
Symbol VIH VIL VOH IOL IHI ILO Ron Parameter Input High Voltage Asynch GTL+ Input Low Voltage Asynch. GTL+ Output High Voltage Output Low Current Pin Leakage High Pin Leakage Low Buffer On Resistance Asynch GTL+ 0 N/A N/A N/A N/A 7 0.9*GTLREF VCC 50 100 500 11 Min 1.10*GTLREF Max VCC Unit V V V mA A A Notes1 3, 4, 5 5 2, 3, 4 6, 8 9 10 5, 7
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. All outputs are open-drain. 3. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality specifications in Section 3. 4. The VCC referred to in these specifications refers to instantaneous VCC. 5. This specification applies to the asynchronous GTL+ signal group. 6. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load shown in Figure 8. 7. Refer to the processor I/O Buffer Models for I/V characteristics. 8. Vol max of 0.270 Volts is guaranteed when driving into a test load of 50 as indicated in Figure 8 for the Asynchronous GTL+ signals. 9. Leakage to VSS with pin held at VCC. 10.Leakage to VCC with pin held at 300 mV.
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Table 15. PWRGOOD and TAP Signal Group DC Specifications
Symbol VHYS VT+ VTVOH IOL IHI ILO Ron Parameter Input Hysteresis Input Low to High Threshold Voltage Input High to Low Threshold Voltage Output High Voltage Output Low Current Pin Leakage High Pin Leakage Low Buffer On Resistance Min 200 1/2*(Vcc+VHYS_MIN) 1/2*(Vcc-VHYS_MAX) N/A N/A N/A N/A 8.75 Max 300 1/2*(Vcc+VHYS_MAX) 1/2*(Vcc-VHYS_MIN) VCC 40 100 500 13.75 Unit mV V V V mA A A Notes1 8 5 5 2,3,5 6,7 9 10 4
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. All outputs are open-drain. 3. TAP signal group must comply with the signal quality specifications in Section 3. 4. Refer to I/O Buffer Models for I/V characteristics. 5. The VCC referred to in these specifications refers to instantaneous VCC. 6. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load shown if Figure 8. 7. Vol max of 0.320 Volts is guaranteed when driving into a test load of 50 Ohms as indicated in Figure 8 for the TAP Signals. 8. VHYS represents the amount of hysteresis, nominally centered about 1/2 Vcc for all TAP inputs. 9. Leakage to VSS with pin held at VCC. 10.Leakage to VCC with pin held at 300 mV.
Table 16. ITPCLKOUT[1:0] DC Specifications
Symbol Ron Parameter Buffer On Resistance Min 27 Max 46 Unit Notes1 2,3
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. These parameters are not tested and are based on design simulations. 3. See Figure 7 for ITPCLKOUT[1:0] output buffer diagram.
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Figure 7. ITPCLKOUT[1:0] Output Buffer Diagram
Vcc
Ron
To Debug Port
Processor Package
Rext
NOTES: 1. See Table 16 for range of Ron. 2. The Vcc referred to in this figure is the instantaneous Vcc. 3. Refer to the appropriate platform design guidelines for the value of Rext.
Table 17. BSEL [1:0] and VID[4:0] DC Specifications
Symbol Ron (BSEL) Ron (VID) IHI Parameter Buffer On Resistance Min 9.2 Max 14.3 Unit A Notes1 2
Buffer On Resistance Pin Leakage Hi
7.8 N/A
12.8 100
2 3
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. These parameters are not tested and are based on design simulations. 3. Leakage to Vss with pin held at 2.50 V.
2.12
AGTL+ System Bus Specifications
Routing topology recommendations may be found in the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide. Termination resistors are not required for most AGTL+ signals, as these are integrated into the processor silicon. Valid high and low levels are determined by the input buffers which compare a signal's voltage with a reference voltage called GTLREF (known as VREF in previous documentation). Table 18 lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits. It is important that the system board impedance is held to the specified tolerance, and that the intrinsic trace capacitance
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for the AGTL+ signal group traces is known and well-controlled. For more details on platform design see the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide.
Table 18. AGTL+ Bus Voltage Definitions
Symbol GTLREF RTT COMP[1:0] Parameter Bus Reference Voltage Termination Resistance COMP Resistance Min 2/3 VCC -2% 45 50.49 Typ 2/3 VCC 50 51 Max 2/3 VCC +2% 55 51.51 Units V Notes1 2, 3, 6 4 5
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The tolerances for this specification have been stated generically to enable the system designer to calculate the minimum and maximum values across the range of VCC. 3. GTLREF should be generated from VCC by a voltage divider of 1% tolerance resistors or 1% tolerance matched resistors. Refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for implementation details. 4. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Refer to processor I/O buffer models for I/V characteristics. 5. COMP resistance must be provided on the system board with 1% tolerance resistors. See the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for implementation details. 6. The VCC referred to in these specifications is the instantaneous VCC.
2.13
System Bus AC Specifications
The processor system bus timings specified in this section are defined at the processor core (pads). See Section 5.2 for the Mobile Intel Pentium 4 Processor-M pin signal definitions. Table 19 through Table 26 list the AC specifications associated with the processor system bus. All AGTL+ timings are referenced to GTLREF for both "0" and "1" logic levels unless otherwise specified. The timings specified in this section should be used in conjunction with the I/O buffer models provided by Intel. These I/O buffer models, which include package information, are available for the Mobile Intel Pentium 4 Processor-M in IBIS format. AGTL+ layout guidelines are also available in the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide. Unless specified otherwise, all Mobile Intel Pentium 4 Processor-M AC specifications are at TJ = 100C. Care should be taken to read all notes associated with a particular timing parameter.
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Table 19. System Bus Differential Clock Specifications
T# Parameter System Bus Frequency T1: BCLK[1:0] Period T2: BCLK[1:0] Period Stability T3: BCLK[1:0] High Time T4: BCLK[1:0] Low Time T5: BCLK[1:0] Rise Time T6: BCLK[1:0] Fall Time 3.94 3.94 175 175 5 5 10.0 Min Nom Max 100 10.2 200 6.12 6.12 700 700 Unit MHz ns ps ns ns ps ps 10 10 10 10 4 4 10 2 3 Figure Notes1
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The period specified here is the average period. A given period may vary from this specification as governed by the period stability specification (T2). 3. In this context, period stability is defined as the worst case timing difference between successive crossover voltages. In other words, the largest absolute difference between adjacent clock periods must be less than the period stability. 4. Slew rate is measured between the 35% and 65% points of the clock swing (VL to VH).
.
Table 20. System Bus Common Clock AC Specifications
T# Parameter T10: Common Clock Output Valid Delay T11: Common Clock Input Setup Time T12: Common Clock Input Hold Time T13: RESET# Pulse Width Min 0.12 0.65 0.40 1 10 Max 1.55 Unit ns ns ns ms Figure 12 12 12 13 Notes1,2,3 4 5 5 6, 7, 8
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Not 100% tested. Specified by design characterization. 3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the processor core. 4. Valid delay timings for these signals are specified into the test circuit described in Figure 8 and with GTLREF at 2/3 VCC 2%. 5. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate of 0.4 V/ns to 4.0 V/ns. 6. RESET# can be asserted asynchronously, but must be deasserted synchronously. 7. This should be measured after VCC and BCLK[1:0] become stable. 8. Maximum specification applies only while PWRGOOD is asserted.
.
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Table 21. System Bus Source Synch AC Specifications AGTL+ Signal Group
T# Parameter T20: Source Synchronous Data Output Valid Delay (first data/address only) T21: TVBD: Source Synchronous Data Output Valid Before Strobe T22: TVAD: Source Synchronous Data Output Valid After Strobe T23: TVBA: Source Synchronous Address Output Valid Before Strobe T24: TVAA: Source Synchronous Address Output Valid After Strobe T25: TSUSS: Source Synchronous Input Setup Time to Strobe T26: THSS: Source Synchronous Input Hold Time to Strobe T27: TSUCC: Source Synchronous Input Setup Time to BCLK[1:0] T28: TFASS: First Address Strobe to Second Address Strobe T29: TFDSS: First Data Strobe to Subsequent Strobes T30: Data Strobe `n' (DSTBN#) Output valid Delay T31: Address Strobe Output Valid Delay 8.80 2.27 Min 0.20 0.85 0.85 1.88 1.88 0.21 0.21 0.65 1/2 n/4 10.20 4.23 Typ Max 1.20 Unit ns ns ns ns ns ns ns ns BCLK BCLK ns ns Figure 14, 15 15 15 14 14 14, 15 14, 15 14, 15 14 15 15 14 Notes1,2,3,4 5 5, 8 5, 9 5, 8 5, 9 6 6 7 10 11, 12 13
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. Not 100% tested. Specified by design characterization. 3. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source synchronous data signals are referenced to the falling edge of their associated data strobe. Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe. All source synchronous AGTL+ signal timings are referenced to GTLREF at the processor core. 4. Unless otherwise noted these specifications apply to both data and address timings. 5. Valid delay timings for these signals are specified into the test circuit described in Figure 8 and with GTLREF at 2/3 VCC 2%. 6. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate of 0.3 V/ns to 4.0V /ns. 7. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each respective strobe. 8. This specification represents the minimum time the data or address will be valid before its strobe. Refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for more information on the definitions and use of these specifications. 9. This specification represents the minimum time the data or address will be valid after its strobe. Refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for more information on the definitions and use of these specifications. 10.The rising edge of ADSTB# must come approximately 1/2 BCLK period (5 ns) after the falling edge of ADSTB#. 11.For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively. 12.The second data strobe (falling edge of DSTBn#) must come approximately 1/4 BCLK period (2.5 ns) after the first falling edge of DSTBp#. The third data strobe (falling edge of DSTBp#) must come approximately 2/4 BCLK period (5 ns) after the first falling edge of DSTBp#. The last data strobe (falling edge of DSTBn#) must come approximately 3/4 BCLK period (7.5 ns) after the first falling edge of DSTBp#. 13.This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.
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Table 22. Miscellaneous Signals AC Specifications
T# Parameter T35: Asynch GTL+ Input Pulse Width T36: PWRGOOD to RESET# de-assertion time T37: PWRGOOD Inactive Pulse Width T38: PROCHOT# pulse width T39: THERMTRIP# to Vcc Removal T40: FERR# Valid Delay from STPCLK# deassertion 0 Min 2 1 10 500 0.5 5 10 Max Unit BCLKs ms BCLKs us s BCLKs 16 16 18 19 20 4 5 Figure Notes1,2,3,6
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. All AC timings for the Asynch GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage. All Asynch GTL+ signal timings are referenced at GTLREF. PWRGOOD is referenced to the BCLK0 rising edge at 0.5*VCC 3. These signals may be driven asynchronously. 4. Refer to the PWRGOOD definition for more details regarding the behavior of this signal. 5. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the assertion and before the deassertion of PROCHOT# for the processor to complete current instruction execution. This specification refers to PROCHOT# when asserted by the processor. There are no pulse width requirements for when PROCHOT# is asserted by the system. 6. See Section 7.2 for additional timing requirements for entering and leaving the low power states.
Table 23. System Bus AC Specifications (Reset Conditions)
T# Parameter T45: Reset Configuration Signals (A[31:3]#, BR0#, INIT#, SMI#) Setup Time T46: Reset Configuration Signals (A[31:3]#, BR0#, INIT#, SMI#) Hold Time NOTES: 1. Before the deassertion of RESET#. 2. After clock that deasserts RESET#. Min 4 2 20 Max Unit BCLKs BCLKs Figure 13 13 1 2 Notes
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Table 24. TAP Signals AC Specifications
Parameter T55: TCK Period T56: TCK Rise Time T57: TCK Fall Time T58: TMS Rise Time T59: TMS Fall Time T61: TDI Setup Time T62: TDI Hold Time T63: TDO Clock to Output Delay T64: TRST# Assert Time 2 0 3 3.5 Min 60.0 10.0 10.0 8.5 8.5 Max Unit ns ns ns ns ns ns ns ns TCK Figure 9 9 9 9 9 21 21 21 18 4 4 4 4, 9 5, 7 5, 7 6 8, 9 Notes1,2,3
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Not 100% tested. Specified by design characterization. 3. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*VCC at the processor pins. All TAP signal timings (TMS, TDI, etc) are referenced at 0.5*VCC at the processor pins. 4. Rise and fall times are measured from the 20% to 80% points of the signal swing. 5. Referenced to the rising edge of TCK. 6. Referenced to the falling edge of TCK. 7. Specifications for a minimum swing defined between TAP VT- to VT+. This assumes a minimum edge rate of 0.5 V/ns 8. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor. 9. It is recommended that TMS be asserted while TRST# is being deasserted.
Table 25. ITPCLKOUT[1:0] AC Specifications
Parameter T65: ITPCLKOUT Delay T66: Slew Rate T67: ITPCLKOUT[1:0] High Time T68: ITPCLKOUT[1:0] Low Time Min 400 2 3.89 3.89 5 5 Typ Max 560 8 6.17 6.17 Unit ps V/ns ns ns Figure 22 Notes1,2 3
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. These parameters are not tested and are based on design simulations. 3. This delay is from rising edge of BCLK0 to the falling edge of ITPCLK0.
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.
Table 26. Stop Grant/Sleep/Deep Sleep/Enhanced Intel SpeedStep Technology AC Specifications
T# Parameter T70: SLP# Signal Hold Time from Stop Grant Cycle Completion T71: Input Signals Stable to SLP# Assertion T72: SLP# to DPSLP# Assertion T73: Deep Sleep PLL Lock Latency T74: SLP# Hold Time from PLL Lock T75: STPCLK# Hold Time from SLP# Deassertion T76: Input Signal Hold Time from SLP# Deassertion T77: VID[4:0] Output Valid Delay from DPSLP# Assertion Min 100 10 10 0 0 10 10 0 10 30 Max Unit BCLKs BCLKs BCLKs s ns BCLKs BCLKs s Figure 23 23, 24 23 23 23 23 23, 24 24 2 1 Notes
NOTES: 1. Input signals other than RESET# must be held constant in the Sleep state. 2. The BCLK can be stopped after DPSLP# is asserted. The BCLK must be turned on and within specification before DPSLP# is deasserted.
.
2.14
Processor AC Timing Waveforms
The following figures are used in conjunction with the AC timing tables, Table 19 through Table 26. For Figure 9 through Figure 24, the following apply:
NOTES: 1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the processor core. 2. All source synchronous AC timings for AGTL+ signals are referenced to their associated strobe (address or data) at GTLREF. Source synchronous data signals are referenced to the falling edge of their associated data strobe. Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe. All source synchronous AGTL+ signal timings are referenced at GTLREF at the processor core silicon. 3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at VCROSS. All AGTL+ strobe signal timings are referenced at GTLREF at the processor core silicon. 4. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*VCC at the processor pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.5*VCC at the processor pins.
The circuit used to test the AC specifications is shown in Figure 8.
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Figure 8. AC Test Circuit
VCC VCC 420 mils, 50 ohms, 169 ps/in 2.4nH 1.2pF
AC Timings test measurements made here.
Rload= 50 ohms
Figure 9. TCK Clock Waveform
V2 V1 V3
tr = T56, T58 (Rise Time) tf = T57, T59 (Fall Time) tp = T55 (TCK Period)
V1,V2: For rise and fall times, TCK is measured between 20% to 80% points on the waveform V3: TCK is referenced to 0.5*Vcc
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.
Figure 10. Differential Clock Waveform
Tph Overshoot BCLK1 VH Rising Edge Ringback Threshold Region Crossing Voltage Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot Tpl Tp
Tp = T1 (BCLK[1:0] period) T2 = BCLK[1:0] Period stability (not shown) Tph =T3 (BCLK[1:0] pulse high time) Tpl = T4 (BCLK[1:0] pulse low time) T5 = BCLK[1:0] rise time through the threshold region T6 = BCLK[1:0] fall time through the threshold region
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Figure 11. Differential Clock Crosspoint Specification
Crosspoint Specification
650 600 550
Crossing Point (mV) Crossing Point (V)
550 mV 550 + 0.5 (VHavg - 710)
500 450 400
250 + 0.5 (VHavg - 710)
350 300 250
250 mV
200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
VHavg (V) Vhavg (mV)
Figure 12. System Bus Common Clock Valid Delay Timings
T0 BCLK1 BCLK0
TP
T1
T2
Common Clock Signal (@ driver) Common Clock Signal (@ receiver)
valid TQ valid
TP = T10: TCO (Data Valid Output Delay) TQ = T11: TSU (Common Clock Setup) TR = T12: TH (Common Clock Hold Time)
valid TR
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Figure 13. System Bus Reset and Configuration Timings
BCLK
Tt
Reset
Tv Tx Tw
Configuration
A[31:3], SMI#, INIT#, BR[3:0]#
Valid
Tv = T13 (RESET# Pulse Width) Tw = T45 (Reset Configuration Signals Setup TIme) Tx = T46 (Reset Configuration Signals Hold TIme)
Figure 14. Source Synchronous 2X (Address) Timings
T1
2.5 ns 5.0 ns 7.5 ns
T2
BCLK1 BCLK0 ADSTB# (@ driver)
TP TR TH valid TS TJ TH valid TJ
A# (@ driver)
ADSTB# (@ receiver)
TK
A# (@ receiver)
valid TN TM
valid
TH = T23: Source Sync. Address Output Valid Before Address Strobe TJ = T24: Source Sync. Address Output Valid After Address Strobe TK = T27: Source Sync. Input Setup to BCLK TM = T26: Source Sync. Input Hold Time TN = T25: Source Sync. Input Setup Time TP = T28: First Address Strobe to Second Address Strobe TS = T20: Source Sync. Output Valid Delay TR = T31: Address Strobe Output Valid Delay
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Figure 15. Source Synchronous 4X Timings
T0
2.5 ns 5.0 ns 7.5 ns
T1
T2
BCLK1 BCLK0 DSTBp# (@ driver)
TH
DSTBn# (@ driver)
TA TB TA TD
D# (@ driver)
TJ
DSTBp# (@ receiver)
DSTBn# (@ receiver)
TC
D# (@ receiver)
TE TG TE TG
TA = T21: Source Sync. Data Output Valid Delay Before Data Strobe TB = T22: Source Sync. Data Output Valid Delay After Data Strobe TC = T27: Source Sync. Setup Time to BCLK TD = T30: Source Sync. Data Strobe 'N' (DSTBN#) Output Valid Delay TE = T25: Source Sync. Input Setup Time TG = T26: Source Sync. Input Hold Time TH = T29: First Data Strobe to Subsequent Strobes TJ = T20: Source Sync. Data Output Valid Delay
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Figure 16. Power Up Sequence
BCLK Vcc PWRGOOD
Tc Td
RESET# VCCVID
Ta Tb
VID_GOOD VID[4:0], BSEL[1:0]
Ta= 1us minimum (VCCVID > 1V to VID_GOOD high) Tb= 50ms maximum (VID_GOOD to Vcc valid maximum time) Tc= T37 (PWRGOOD inactive pulse width) Td= T36 (PWRGOOD to RESET# de-assertion time) Note: VID_GOOD is not a processor signal. This signal is routed to the output enable pin of the voltage regluator control silicon. For more information on implementation refer to the Intel Mobile Northwood Processor and Intel 845MP Platform RDDP.
Figure 17. Power Down Sequence
Vcc PWRGOOD VCCVID
VID_GOOD VID[4:0]
Note: VID_GOOD is not a processor signal. This signal is routed to the output enable pin of the voltage regluator control silicon. For more information on implementation refer to the Intel Mobile Northwood Processor and Intel 845MP Platform RDDP. 1. This timing diagram is not intended to show specific times. Instead a general ordering of events with respect to time should be observed. 2. When VCCVID is less than 1V, VID_GOOD must be low. 3. Vcc must be disabled before VID[4:0] becomes invalid. 4. VCCVID and Vcc regulator can be disabled simultaneously
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Figure 18. Test Reset Timings
TRST# 1.25V Tq Tq = T37 (TRST# Pulse Width) Width), V=GTLREF T38 (PROCHOT# Pulse
PCB-773
Tq = T64 (TRST# Pulse Width), V=0.5*Vcc
Figure 19. THERMTRIP# to Vcc Timing
T39
THERMTRIP# Vcc
T39 < 0.5 seconds Note: THERMTRIP# is undefined when RESET# is active
Figure 20. FERR#/PBE# Valid Delay Timing
BCLK system bus STPCLK#
Ta
SG Ack
FERR#/ PBE#
FERR#
undefined
PBE#
undefined
FERR#
Ta = T40 (FERR# Valid Delay from STPCLK# Deassertion) Note: FERR#/PBE# is undefined from STPCLK# assertion until the stop grant acknowledge is driven on the processor system bus. FERR#/PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined regions the PBE# signal is driven. FERR# is driven at all other times.
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Figure 21. TAP Valid Delay Timing
V TCK Tx Signal Ts Th
V Valid
Tx = T63 (Valid Time) Ts = T61 (Setup Time) Th = T62 (Hold Time) V = 0.5 * Vcc
Figure 22. ITPCLKOUT Valid Delay Timing
Tx
BCLK ITPCLKOUT
T65 = Tx = BCLK input to ITPCLKOUT output delay
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Figure 23. Stop Grant/Sleep/Deep Sleep Timing
Normal BCLK[1:0] Stop Grant Sleep Deep Sleep Sleep Stop Grant Normal
DPSLP# Tv STPCLK# Ty CPU bus stpgnt Tt SLP# Tu Compatibility Signals Changing Frozen Tz Changing
V0011-02
Tw
Tx
Tt = T70 (Stop Grant Acknowledge Bus Cycle Completion to SLP# Assertion Delay) Tu = T71 (Input Signals Stable to SLP# assertion requirement) Tv = T72 (SLP# to DPSLP# assertion) Tw = T73 (Deep Sleep PLL lock latency) Tx = T74 (SLP# Hold Time) Ty = T75 (STPCLK# Hold Time) Tz = T76 (Input Signal Hold Time)
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Figure 24. Enhanced Intel SpeedStep Technology/Deep Sleep Timing
BCLK[1:0]
SLP# TX DPSLP# TS GHI# GHI# stable
Th
VID[4:0]
previous VID
next VID
V0036-04
TS = T71 (GHI# Input Setup to SLP# Assertion) Th = T76 (GHI# Input signal Hold Time from SLP# De-assertion) TX = T77 (VID[4:0] Output Valid Delay from DPSLP# Assertion)
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3.
System Bus Signal Quality Specifications
Source synchronous data transfer requires the clean reception of data signals and their associated strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines. Excessive signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity and can cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and undershoot can cause timing degradation due to the build up of inter-symbol interference (ISI) effects. For these reasons, it is important that the designer work to achieve a solution that provides acceptable signal quality across all systematic variations encountered in volume manufacturing. This section documents signal quality metrics used to derive topology and routing guidelines through simulation and for interpreting results for signal quality measurements of actual designs.
3.1
System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines
Table 27 describes the signal quality specifications at the processor pads for the processor system bus clock (BCLK) signals. Figure 25 describes the signal quality waveform for the system bus clock at the processor pads.
Table 27. BCLK Signal Quality Specifications
Parameter Min Max Unit Figure Notes1
BCLK[1:0] Overshoot BCLK[1:0] Undershoot BCLK[1:0] Ringback Margin BCLK[1:0] Threshold Region
N/A N/A 0.20 N/A
0.30 0.30 N/A 0.10
V V V V
25 25 25 25 2
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M frequencies. 2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This specification is an absolute value.
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Figure 25. BCLK Signal Integrity Waveform
Overshoot BCLK1 VH Rising Edge Ringback Threshold Region Crossing Voltage Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot
3.2
System Bus Signal Quality Specifications and Measurement Guidelines
Various scenarios have been simulated to generate a set of AGTL+ layout guidelines which are available in the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide. Table 28 and Table 29 provides the signal quality specifications for all processor signals for use in simulating signal quality at the processor core silicon (pads). Mobile Intel Pentium 4 Processor-M maximum allowable overshoot and undershoot specifications for a given duration of time are detailed in Table 30 through Table 33. Figure 26 shows the system bus ringback tolerance for low-to-high transitions and Figure 27 shows ringback tolerance for high-to-low transitions.
Table 28. Ringback Specifications for AGTL+ and Asynchronous GTL+ Signal Groups
Signal Group Transition Maximum Ringback (with Input Diodes Present) Unit Figure Notes
All Signals All Signals
0 1
1 0
GTLREF + 10% GTLREF - 10%
V V
26 27
1,2,3,4,5,6,7 1,2,3,4,5,6,7
NOTES: 1. All signal integrity specifications are measured at the processor silicon (pads). 2. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M frequencies. 3. Specifications are for the edge rate of 0.3 - 4.0 V/ns. 4. All values specified by design characterization. 5. Please see Section 3.3 for maximum allowable overshoot. 6. Ringback between GTLREF + 10% and GTLREF - 10% is not supported. 7. Intel recommends simulations not exceed a ringback value of GTLREF +/- 200 mV to allow margin for other sources of system noise.
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Table 29. Ringback Specifications for PWRGOOD Input and TAP Signal Groups
Maximum Ringback (with Input Diodes Present) Notes
Signal Group
Transition
Unit
Figure
TAP and PWRGOOD TAP and PWRGOOD
01 10
Vt+(max) TO Vt-(max) Vt-(min) TO Vt+(min)
V V
28 29
1,2,3,4 1,2,3,4
NOTES: 1. All signal integrity specifications are measured at the processor silicon. 2. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M frequencies. 3. Please see Section 3.3 for maximum allowable overshoot. 4. Please see Section 2.11 for the DC specifications.
Figure 26. Low-to-High System Bus Receiver Ringback Tolerance
VCC
+10% GTLREF GTLREF -10% GTLREF
Noise Margin
VSS
Figure 27. High-to-Low System Bus Receiver Ringback Tolerance
VCC
+10% GTLREF GTLREF -10% GTLREF
Noise Margin
VSS
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Figure 28. Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers
Vcc
Threshold Region to switch receiver to a logic 1.
Vt+ (max) Vt+ (min) 0.5 * Vcc Vt- (max)
Allowable Ringback
Vss
Figure 29. High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers
Vcc
Allowable Ringback
Vt+ (min) 0.5 * Vcc Vt- (max) Vt- (min)
Threshold Region to switch receiver to a logic 0.
Vss
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3.3
System Bus Signal Quality Specifications and Measurement Guidelines
Overshoot/Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage (or below VSS) as shown in Figure 30. The overshoot guideline limits transitions beyond VCC or VSS due to the fast signal edge rates. The processor can be damaged by repeated overshoot or undershoot events on any input, output, or I/O buffer if the charge is large enough (i.e., if the over/undershoot is great enough). Determining the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse direction, and the activity factor (AF). Permanent damage to the processor is the likely result of excessive overshoot/undershoot. When performing simulations to determine impact of overshoot and undershoot, ESD diodes must be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide overshoot or undershoot protection. ESD diodes modelled within Intel I/O buffer models do not clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models are being used to characterize the Mobile Intel Pentium 4 Processor-M system bus, care must be taken to ensure that ESD models do not clamp extreme voltage levels. Intel I/O buffer models also contain I/O capacitance characterization. Therefore, removing the ESD diodes from an I/O buffer model will impact results and may yield excessive overshoot/undershoot.
3.3.1
3.3.2
Overshoot/Undershoot Magnitude
Magnitude describes the maximum potential difference between a signal and its voltage reference level. For the Mobile Intel Pentium 4 Processor-M both are referenced to VSS. It is important to note that overshoot and undershoot conditions are separate and their impact must be determined independently. Overshoot/undershoot magnitude levels must observe the absolute maximum specifications listed in Table 30 through Table 33. These specifications must not be violated at any time regardless of bus activity or system state. Within these specifications are threshold levels that define different allowed pulse durations. Provided that the magnitude of the overshoot/undershoot is within the absolute maximum specifications, the pulse magnitude, duration and activity factor must all be used to determine if the overshoot/undershoot pulse is within specifications.
3.3.3
Overshoot/Undershoot Pulse Duration
Pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/ undershoot reference voltage (maximum overshoot = 1.700 V, maximum undershoot = -0.400 V). The total time could encompass several oscillations above the reference voltage. Multiple overshoot/undershoot pulses within a single overshoot/undershoot event may need to be measured to determine the total pulse duration.
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System Bus Signal Quality Specifications
Note:
Oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot pulse duration.
3.3.4
Activity Factor
Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a clock. Since the highest frequency of assertion of any signal is every other clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs EVERY OTHER clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs one time in every 200 clock cycles. For source synchronous signals (address, data, and associated strobes), the activity factor is in reference to the strobe edge, since the highest frequency of assertion of any source synchronous signal is every active edge of its associated strobe. An AF = 1 indicates that the specific overshoot (undershoot) waveform occurs every strobe cycle. The specifications provided in Table 30 through Table 33 show the maximum pulse duration allowed for a given overshoot/undershoot magnitude at a specific activity factor. Each table entry is independent of all others, meaning that the pulse duration reflects the existence of overshoot/ undershoot events of that magnitude ONLY. A platform with an overshoot/undershoot that just meets the pulse duration for a specific magnitude where the AF < 1, means that there can be no other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the event occurs at all times and no other events can occur).
Note: Note: Note:
1: Activity factor for AGTL+ signals is referenced to BCLK[1:0] frequency. 2: Activity factor for source synchronous (2x) signals is referenced to ADSTB[1:0]#. 3: Activity factor for source synchronous (4x) signals is referenced to DSTBP[3:0]# and DSTBN[3:0]#.
3.3.5
Reading Overshoot/Undershoot Specification Tables
The overshoot/undershoot specification for the Mobile Intel Pentium 4 Processor-M is not a simple single value. Instead, many factors are needed to determine what the over/undershoot specification is. In addition to the magnitude of the overshoot, the following parameters must also be known: the width of the overshoot (as measured above VCC) and the activity factor (AF). To determine the allowed overshoot for a particular overshoot event, the following must be done: 1. Determine the signal group a particular signal falls into. If the signal is an AGTL+ signal operating in the common clock domain, use Table 32. For AGTL+ signals operating in the 2x source synchronous domain, use Table 31. For AGTL+ signals operating in the 4x source synchronous domain, use Table 30. Finally, all other signals reside in the 100MHz domain (asynchronous GTL+, TAP, etc.) and are referenced in Table 33. 2. Determine the magnitude of the overshoot (relative to VSS). 3. Determine the activity factor (how often does this overshoot occur?) 4. Next, from the appropriate specification table, determine the maximum pulse duration (in nanoseconds) allowed. 5. Compare the specified maximum pulse duration to the signal being measured. If the pulse duration measured is less than the pulse duration shown in the table, then the signal meets the specifications.
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The above procedure is similar for undershoot after the undershoot waveform has been converted to look like an overshoot. Undershoot events must be analyzed separately from overshoot events as they are mutually exclusive.
3.3.6
Conformance Determination to Overshoot/Undershoot Specifications
The overshoot/undershoot specifications listed in the following tables specify the allowable overshoot/undershoot for a single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events that each have their own set of parameters (duration, AF and magnitude). While each overshoot on its own may meet the overshoot specification, when you add the total impact of all overshoot events, the system may fail. A guideline to ensure a system passes the overshoot and undershoot specifications is shown below. 1. Ensure no signal ever exceeds VCC or -0.25 V OR 2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot specifications in the following tables OR 3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse duration for each magnitude and compare the results against the AF = 1 specifications. If all of these worst case overshoot or undershoot events meet the specifications (measured time < specifications) in the table (where AF=1), then the system passes. The following notes apply to Table 30 through Table 33.
NOTES: 1. Absolute Maximum Overshoot magnitude of 1.70 V must never be exceeded. 2. Absolute Maximum Overshoot is measured relative to VSS, Pulse Duration of overshoot is measured relative to VCC. 3. Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to VSS. 4. Ringback below VCC can not be subtracted from overshoots/undershoots. 5. Lesser undershoot does not allocate longer or larger overshoot. 6. OEM's are strongly encouraged to follow Intel provided layout guidelines. 7. All values specified by design characterization.
Table 30. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance
Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 Notes 1,2
1.700 1.650 1.600 1.550 1.500 1.450 1.400 1.350
-0.400 -0.350 -0.300 -0.250 -0.200 -0.150 -0.100 -0.050
0.11 0.24 0.53 1.19 5.00 5.00 5.00 5.00
1.05 2.40 5.00 5.00 5.00 5.00 5.00 5.00
5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00
NOTES: 1. These specifications are measured at the processor core silicon. 2. BCLK period is 10 ns.
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System Bus Signal Quality Specifications
Table 31. Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance
Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 Notes 1,2
1.700 1.650 1.600 1.550 1.500 1.450 1.400 1.350
-0.400 -0.350 -0.300 -0.250 -0.200 -0.150 -0.100 -0.050
0.21 0.48 1.05 2.38 10.00 10.00 10.00 10.00
2.10 4.80 10.00 10.00 10.00 10.00 10.00 10.00
10.00 10.00 10.00 10.00 10.00 10.00 10.00 10.00
NOTES: 1. These specifications are measured at the processor core silicon. 2. BCLK period is 10 ns.
Table 32. Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance
Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 Notes 1,2
1.700 1.650 1.600 1.550 1.500 1.450 1.400 1.350
-0.400 -0.350 -0.300 -0.250 -0.200 -0.150 -0.100 -0.050
0.42 0.96 2.10 4.76 20.00 20.00 20.00 20.00
4.20 9.60 20.00 20.00 20.00 20.00 20.00 20.00
20.00 20.00 20.00 20.00 20.00 20.00 20.00 20.00
NOTES: 1. These specifications are measured at the processor core silicon. 2. BCLK period is 10 ns.
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Table 33. Asynchronous GTL+, PWRGOOD Input, and TAP Signal Groups Overshoot/ Undershoot Tolerance
Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 Notes 1,2
1.700 1.650 1.600 1.550 1.500 1.450 1.400 1.350
-0.400 -0.350 -0.300 -0.250 -0.200 -0.150 -0.100 -0.050
1.26 2.88 6.30 14.28 60.00 60.00 60.00 60.00
12.6 28.8 60.00 60.00 60.00 60.00 60.00 60.00
60.00 60.00 60.00 60.00 60.00 60.00 60.00 60.00
NOTES: 1. These specifications are measured at the processor core silicon. 2. BCLK period is 10 ns.
Figure 30. Maximum Acceptable Overshoot/Undershoot Waveform
Maximum Absolute Overshoot VMAX VCC
Time-dependent Overshoot
GTLREF VOL VSS VMIN Maximum Absolute Undershoot Time-dependent Undershoot
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Package Mechanical Specifications
4.
Package Mechanical Specifications
The Mobile Intel Pentium 4 Processor-M is packaged in a 478 pin Micro-FCPGA package. Different views of the package are shown in Figure 31 through Figure 33. Package dimensions are shown in Table 34.
Figure 31. Micro-FCPGA Package Top and Bottom Isometric Views
PACKAGE KEEPOUT
CAPACITOR AREA
DIE LABEL
TOP VIEW
BOTTOM VIEW
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61
Package Mechanical Specifications
Figure 32. Micro-FCPGA Package Top and Side View
7 (K1) 8 places 5 (K) 4 places SUBSTRATE KEEPOUT ZONE DO NOT CONTACT PACKAGE INSIDE THIS LINE 0.286
A 1.25 MAX (A3)
D1
35 (D)
O 0.32 (B) 478 places
E1 35 (E)
A2 PIN A1 CORNER 2.03 0.08 (A1)
All dimensions in millimeters. Values shown are for reference only.
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Package Mechanical Specifications
Table 34. Micro-FCPGA Package Dimensions
Symbol Param eter A A1 A2 A3 B D E Overall height, top of die to package seating plane Overall height, top of die to PCB surface, including socket(1) Pin length Die height Pin-side capacitor height Pin diameter Package substrate length Package substrate width 0.28 34.9 34.9 Min 1.81 4.69 1.95 0.854 1.25 0.36 35.1 35.1 M ax 2.03 5.15 2.11 Unit mm mm mm mm mm mm mm mm
D1
Die length
12.24 (B0 Step) 11.62 (B0 Step Shrink & C1/D1 Step) 11.93 (B0 Step) 11.34 (B0 Step Shrink & C1/D1 Step) 1.27 5 7 14 <=0.254 478 4.5 0.286 689
mm
E1 e K K1 K3 N Pdie W
Die width Pin pitch Package edge keep-out Package corner keep-out Pin-side capacitor boundary Pin tip radial true position Pin count Allowable pressure on the die for therm al solution Package weight Package Surface Flatness
mm mm mm mm mm mm each kPa g mm
NOTES: 1. All Dimensions are subject to change. Values shown are for reference only. 2. Overall height with socket is based on design dimensions of the Micro-FCPGA package and socket with no thermal solution attached. Values were based on design specifications and tolerances. This dimension is subject to change based on socket design, OEM motherboard design, or OEM SMT process.
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Package Mechanical Specifications
Figure 33. Micro-FCPGA Package - Bottom View
14 (K3)
AF AD AB Y V T P M K H F D B
AE AC AA W U R N L J G E C A 1 3 2 4 5 6 7 8 9 10 11 13 15 17 19 21 23 25 12 14 16 18 20 22 24 26 14 (K3)
25X 1.27 (e)
25X 1.27 (e)
NOTE: All dimensions in millimeters. Values shown are for reference only.
4.1
Processor Pin-Out
Figure 34 shows the top view pinout of the Mobile Intel Pentium 4 Processor-M.
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Package Mechanical Specifications
Figure 34.
1 2
The Coordinates of the Processor Pins as Viewed From the Top of the Package.
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
THERMTRIP# VSS VSSSE VCCSE NSE NSE VSS SMI# GHI# FERR#/ PBE# NC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS NC D#[2] VSS D#[3] VSS
A B
VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D#[0] D#[1] VSS D#[6] D#[9] VSS
B
IGNNE#
THRMD A
C
TDI VSS PROCHOT# THRMDC VSS A20M# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC D#[4] VSS D#[7] D#[8] VSS D#[12]
C D
LINT0 BPRI# VSS TCK TDO VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS D#[5] D#[13] VSS D#[15] D#[23] DSTBN# VSS [0]
D E
VSS DEFER# HITM# VSS LINT1 TRST# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC DBI#[0]
E
D#[17] D#[21] VSS
F
RS#[0] VSS HIT# RS#[2] VSS GTLREF TMS VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC GTLREF DSTBP# VSS [0] VSS D#[19] D#[20] VSS D#[22]
F G
G
ADS# BNR# VSS LOCK# RS#[1] VSS D#[10] D#[18] VSS DBI#[1] D#[25]
H
VSS DRDY# REQ#[4] VSS DBSY# BR0# D#[11] D#[16] VSS D#[26] D#[31] VSS
H J
VSS DP#[0]
J
REQ#[0] VSS REQ#[3]REQ#[2] VSS TRDY# D#[14] VSS DSTBP# D#[29] [1] VSS
K
A#[6] A#[3] VSS A#[4] REQ#[1] VSS VSS DSTBN# D#[30] [1] DP#[1] DP#[2]
K L
L
VSS A#[9] A#[7] VSS ADSTB#[0] A#[5] D#[24] D#[28] VSS COMP[0] DP#[3] VSS
M
A#[13] VSS A#[10] A#[11] VSS A#[8] D#[27] VSS D#[32] D#[35] VSS D#[37]
M N
A#[12] A#[14] VSS A#[15] A#[16] VSS
N P
COMP[1] VSS A#[19] A#[20] VSS A#[24]
TOP VIEW
VSS
D#[33] D#[36]
VSS
D#[39] D#[38]
D#[34]
VSS
DSTBP# D#[41] [2] VSS
P
VSS DBI#[2]
R
VSS A#[18] A#[21] VSS ADSTB#[1] A#[28]
D#[40] DSTBN# [2] VSS
R
D#[43] D#[42] VSS
T
A#[17] A#[22] VSS A#[26] A#[30] VSS TESTHI 8 D#[46] D#[47] VSS D#[45] D#[44]
T U
D#[52] VSS D#[50] D#[49] VSS D#[48]
U
A#[23] VSS A#[25] A#[31] VSS
V
VSS A#[27] A#[32] VSS AP#[1] MCERR# DBI#[3] D#[53] VSS D#[54] D#[51] VSS
V W
D#[57] D#[55]
W
A#[29] A#[33] VSS TESTHI INIT# 9 VSS VSS DSTBN#[3] DSTBP# VSS [3] D#[60] VSS D#[58] D#[59]
Y
A#[34] VSS TESTHI VSS 10 STPCLK# BPM#[3] VSS D#[56]
Y
ITPCLKOUT GTLREF D#[62] VSS [0] VSS VSS
AA
VSS TESTHI1 BINIT# VSS BPM#[4] GTLREF VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS
AA
D#[63] D#[61] VSS
AB
A#[35] RSP# VSS BPM#[5] BPM#[1] VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC ITPCLKOU PWRGOODVSS RESET# SLP# T[1] ITP_CLK0
AB AC
AC
AP#[0] VSS IERR# BPM#[2] VSS BPM#[0] VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS TESTHI3 TESTHI2 VSS TESTHI5 TESTHI4 VSS
AD
VSS NC NC VSS BSEL1 BSEL0 VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCCA VSS VSSA VSS VCCIO_ PLL TESTHI ITP_CL DPSLP# 0 K1 VSS DBR# VSS SKTOC C#
AD AE AF
AE
VID4 VID3 VID2 VID1 VID0 VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC NC VSS
AF
VSS VCC NC VCCVID VCC VSS VCC VSS VCC VSS VCC VSS
VCC VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC BCLK[0] BCLK[1]
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
VSS
VCC
Other
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Package Mechanical Specifications
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Pin Listing and Signal Definitions
5.
5.1
Pin Listing and Signal Definitions
Mobile Intel Pentium 4 Processor-M Pin Assignments
Section 5.1 contains the pin list for the Mobile Intel Pentium 4 Processor-M in Table 35 and Table 36. Table 35 is a listing of all processor pins ordered alphabetically by pin name. Table 36 is also a listing of all processor pins but ordered by pin number.
Mobile Intel Pentium 4 Processor-M
67
Pin Listing and Signal Definitions
Table 35. Table 35.
Pin Name
Pin Listing by Pin Name
Pin Number Signal Buffer Type Direction
Pin Listing by Pin Name
Pin Number Signal Buffer Type Direction
Pin Name
AP#[0] AP#[1] BCLK[0] BCLK[1] BINIT# BNR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPRI# BR0# BSEL0 BSEL1 COMP[0] COMP[1] D#[0] D#[01] D#[02] D#[03] D#[04] D#[05] D#[06] D#[07] D#[08] D#[09] D#[10] D#[11] D#[12] D#[13] D#[14] D#[15] D#[16] D#[17] D#[18] D#[19] D#[20]
AC1 V5 AF22 AF23 AA3 G2 AC6 AB5 AC4 Y6 AA5 AB4 D2 H6 AD6 AD5 L24 P1 B21 B22 A23 A25 C21 D22 B24 C23 C24 B25 G22 H21 C26 D23 J21 D25 H22 E24 G23 F23 F24
Common Clock Common Clock Bus Clock Bus Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch
Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Output Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
A#[03] A#[04] A#[05] A#[06] A#[07] A#[08] A#[09] A#[10] A#[11] A#[12] A#[13] A#[14] A#[15] A#[16] A#[17] A#[18] A#[19] A#[20] A#[21] A#[22] A#[23] A#[24] A#[25] A#[26] A#[27] A#[28] A#[29] A#[30] A#[31] A#[32] A#[33] A#[34] A#[35] A20M# ADS# ADSTB#[0] ADSTB#[1]
K2 K4 L6 K1 L3 M6 L2 M3 M4 N1 M1 N2 N4 N5 T1 R2 P3 P4 R3 T2 U1 P6 U3 T4 V2 R6 W1 T5 U4 V3 W2 Y1 AB1 C6 G1 L5 R5
Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Asynch GTL+ Common Clock Source Synch Source Synch
Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output
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Table 35.
Pin Name
Pin Listing by Pin Name
Pin Number Signal Buffer Type Direction
Table 35.
Pin Name
Pin Listing by Pin Name
Pin Number Signal Buffer Type Direction
D#[21] D#[22] D#[23] D#[24] D#[25] D#[26] D#[27] D#[28] D#[29] D#[30] D#[31] D#[32] D#[33] D#[34] D#[35] D#[36] D#[37] D#[38] D#[39] D#[40] D#[41] D#[42] D#[43] D#[44] D#[45] D#[46] D#[47] D#[48] D#[49] D#[50] D#[51] D#[52] D#[53] D#[54] D#[55] D#[56] D#[57] D#[58] D#[59]
E25 F26 D26 L21 G26 H24 M21 L22 J24 K23 H25 M23 N22 P21 M24 N23 M26 N26 N25 R21 P24 R25 R24 T26 T25 T22 T23 U26 U24 U23 V25 U21 V22 V24 W26 Y26 W25 Y23 Y24
Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch
Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
D#[60] D#[61] D#[62] D#[63] DBI#[0] DBI#[1] DBI#[2] DBI#[3] DBR# DBSY# DEFER# DP#[0] DP#[1] DP#[2] DP#[3] DPSLP# DRDY# DSTBN#[0] DSTBN#[1] DSTBN#[2] DSTBN#[3] DSTBP#[0] DSTBP#[1] DSTBP#[2] DSTBP#[3] FERR#/PBE# GHI# GTLREF GTLREF GTLREF GTLREF HIT# HITM# IERR# IGNNE# INIT# ITPCLKOUT[0] ITPCLKOUT[1] ITP_CLK0
Y21 AA25 AA22 AA24 E21 G25 P26 V21 AE25 H5 E2 J26 K25 K26 L25 AD25 H2 E22 K22 R22 W22 F21 J23 P23 W23 B6 A6 AA21 AA6 F20 F6 F3 E3 AC3 B2 W5 AA20 AB22 AC26
Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Power/Other Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Asynch GTL+ Common Clock Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Asynch AGL+ Asynch GTL+ Power/Other Power/Other Power/Other Power/Other Common Clock Common Clock Common Clock Asynch GTL+ Asynch GTL+ Power/Other Power/Other TAP
Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input Input Input Input Input Input/Output Input/Output Output Input Input Output Output input
Mobile Intel Pentium 4 Processor-M Datasheet
69
Pin Listing and Signal Definitions
Table 35.
Pin Name
Pin Listing by Pin Name
Pin Number Signal Buffer Type Direction
Table 35.
Pin Name
Pin Listing by Pin Name
Pin Number Signal Buffer Type Direction
ITP_CLK1 LINT0 LINT1 LOCK# MCERR# NC NC NC NC NC NC NC NC PROCHOT# PWRGOOD REQ#[0] REQ#[1] REQ#[2] REQ#[3] REQ#[4] RESET# RS#[0] RS#[1] RS#[2] RSP# SKTOCC# SLP# SMI# STPCLK# TCK TDI TDO TESTHI0 TESTHI1 TESTHI2 TESTHI3 TESTHI4 TESTHI5 TESTHI8
AD26 D1 E5 G4 V6 A22 A7 AD2 AD3 AE21 AF3 AF24 AF25 C3 AB23 J1 K5 J4 J3 H3 AB25 F1 G5 F4 AB2 AF26 AB26 B5 Y4 D4 C1 D5 AD24 AA2 AC21 AC20 AC24 AC23 U6
TAP Asynch GTL+ Asynch GTL+ Common Clock Common Clock
input Input Input Input/Output Input/Output
TESTHI9 TESTHI10 THERMDA THERMDC THERMTRIP# TMS TRDY# TRST# VCC VCC VCC VCC VCC
W4 Y3 B3 C4 A2 F7 J6 E6 A10 A12 A14 A16 A18 A20 A8 AA10 AA12 AA14 AA16 AA18 AA8 AB11 AB13 AB15 AB17 AB19 AB7 AB9 AC10 AC12 AC14 AC16 AC18 AC8 AD11 AD13 AD15 AD17 AD19
Power/Other Power/Other Power/Other Power/Other Asynch GTL+ TAP Common Clock TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Input Input
Output Input Input Input
Asynch GTL+ Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch Common Clock Common Clock Common Clock Common Clock Common Clock Power/Other Asynch GTL+ Asynch GTL+ Asynch GTL+ TAP TAP TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input Input Output Input Input Input Input Input Output Input Input Input Input Input Input Input
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
70
Mobile Intel Pentium 4 Processor-M Datasheet
Pin Listing and Signal Definitions
Table 35.
Pin Name
Pin Listing by Pin Name
Pin Number Signal Buffer Type Direction
Table 35.
Pin Name
Pin Listing by Pin Name
Pin Number Signal Buffer Type Direction
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
AD7 AD9 AE10 AE12 AE14 AE16 AE18 AE20 AE6 AE8 AF11 AF13 AF15 AF17 AF19 AF2 AF21 AF5 AF7 AF9 B11 B13 B15 B17 B19 B7 B9 C10 C12 C14 C16 C18 C20 C8 D11 D13 D15 D17 D19
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCA VCCIOPLL VCCSENSE VCCVID VID0 VID1 VID2 VID3 VID4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
D7 D9 E10 E12 E14 E16 E18 E20 E8 F11 F13 F15 F17 F19 F9 AD20 AE23 A5 AF4 AE5 AE4 AE3 AE2 AE1 A11 A13 A15 A17 A19 A21 A24 A26 A3 A9 AA1 AA11 AA13 AA15 AA17
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Input Output Output Output Output Output
Mobile Intel Pentium 4 Processor-M Datasheet
71
Pin Listing and Signal Definitions
Table 35.
Pin Name
Pin Listing by Pin Name
Pin Number Signal Buffer Type Direction
Table 35.
Pin Name
Pin Listing by Pin Name
Pin Number Signal Buffer Type Direction
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AA19 AA23 AA26 AA4 AA7 AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB21 AB24 AB3 AB6 AB8 AC11 AC13 AC15 AC17 AC19 AC2 AC22 AC25 AC5 AC7 AC9 AD1 AD10 AD12 AD14 AD16 AD18 AD21 AD23 AD4 AD8 AE11
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AE13 AE15 AE17 AE19 AE22 AE24 AE26 AE7 AE9 AF1 AF10 AF12 AF14 AF16 AF18 AF20 AF6 AF8 B10 B12 B14 B16 B18 B20 B23 B26 B4 B8 C11 C13 C15 C17 C19 C2 C22 C25 C5 C7 C9
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
72
Mobile Intel Pentium 4 Processor-M Datasheet
Pin Listing and Signal Definitions
Table 35.
Pin Name
Pin Listing by Pin Name
Pin Number Signal Buffer Type Direction
Table 35.
Pin Name
Pin Listing by Pin Name
Pin Number Signal Buffer Type Direction
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
D10 D12 D14 D16 D18 D20 D21 D24 D3 D6 D8 E1 E11 E13 E15 E17 E19 E23 E26 E4 E7 E9 F10 F12 F14 F16 F18 F2 F22 F25 F5 F8 G21 G24 G3 G6 H1 H23 H26
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
H4 J2 J22 J25 J5 K21 K24 K3 K6 L1 L23 L26 L4 M2 M22 M25 M5 N21 N24 N3 N6 P2 P22 P25 P5 R1 R23 R26 R4 T21 T24 T3 T6 U2 U22 U25 U5 V1 V23
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Mobile Intel Pentium 4 Processor-M Datasheet
73
Pin Listing and Signal Definitions
Table 35.
Pin Name
Pin Listing by Pin Name
Pin Number Signal Buffer Type Direction
Table 36. Pin Listing by Pin Number
Pin Number Pin Name Signal Buffer Type Direction
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSA VSSSENSE
V26 V4 W21 W24 W3 W6 Y2 Y22 Y25 Y5 AD22 A4
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output
A25 A26 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11
D#[03] VSS VSS TESTHI1 BINIT# VSS BPM#[4] GTLREF VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS ITPCLKOUT [0] GTLREF D#[62] VSS D#[63] D#[61] VSS A#[35] RSP# VSS BPM#[5] BPM#[1] VSS VCC VSS VCC VSS
Source Synch Power/Other Power/Other Power/Other Common Clock Power/Other Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Common Clock Power/Other Common Clock Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other
Input/Output
Input Input/Output
Input/Output Input
Table 36. Pin Listing by Pin Number
Pin Number Pin Name Signal Buffer Type Direction
AA12 AA13 AA14
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24
THERMTRIP# VSS VSSSENSE VCCSENSE GHI# NC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS NC D#[02] VSS
Asynch GTL+ Power/Other Power/Other Power/Other Asynch GTL+
Output
AA15 AA16
Output Output Input
AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Output Input Input/Output
Input/Output Input/Output
Input/Output Input
Input/Output Input/Output
Source Synch Power/Other
Input/Output
AB9 AB10
74
Mobile Intel Pentium 4 Processor-M Datasheet
Pin Listing and Signal Definitions
Table 36. Pin Listing by Pin Number
Pin Number Pin Name Signal Buffer Type Direction
Table 36. Pin Listing by Pin Number
Pin Number Pin Name Signal Buffer Type Direction
AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22
VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS ITPCLKOUT [1] PWRGOOD VSS RESET# SLP# AP#[0] VSS IERR# BPM#[2] VSS BPM#[0] VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS TESTHI3 TESTHI2 VSS
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Asynch GTL+ Common Clock Power/Other Common Clock Common Clock Power/Other Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input/Output Output Input/Output Input Input Input/Output Output Input
AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9
TESTHI5 TESTHI4 VSS ITP_CLK0 VSS NC NC VSS BSEL1 BSEL0 VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCCA VSS VSSA VSS TESTHI0 DPSLP# ITP_CLK1 VID4 VID3 VID2 VID1 VID0 VCC VSS VCC VSS
Power/Other Power/Other Power/Other TAP Power/Other
Input Input
input
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch GTL+ TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input input Output Output Output Output Output Output Output
Mobile Intel Pentium 4 Processor-M Datasheet
75
Pin Listing and Signal Definitions
Table 36. Pin Listing by Pin Number
Pin Number Pin Name Signal Buffer Type Direction
Table 36. Pin Listing by Pin Number
Pin Number Pin Name Signal Buffer Type Direction
AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22
VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC NC VSS VCCIOPLL VSS DBR# VSS VSS VCC NC VCCVID VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC BCLK[0]
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
AF23 AF24 AF25 AF26 B2 B3 B4 B5 B6 B7 B8 B9
BCLK[1] NC NC SKTOCC# IGNNE# THERMDA VSS SMI# FERR#/PBE# VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D#[0] D#[01] VSS D#[06] D#[09] VSS TDI VSS PROCHOT# THERMDC VSS A20M# VSS VCC VSS VCC
Bus Clock
Input
Power/Other Asynch GTL+ Power/Other Power/Other Asynch GTL+ Asynch AGL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other TAP Power/Other Asynch GTL+ Power/Other Power/Other Asynch GTL+ Power/Other Power/Other Power/Other Power/Other
Output Input
Input Output
Power/Other Power/Other Power/Other Asynch GTL+ Power/Other Power/Other Power/Other Output
B10 B11 B12 B13 B14 B15 B16 B17
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Bus Clock
Input
B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9
Input/Output Input/Output
Input/Output Input/Output
Input
Output
Input
Input
C10
76
Mobile Intel Pentium 4 Processor-M Datasheet
Pin Listing and Signal Definitions
Table 36. Pin Listing by Pin Number
Pin Number Pin Name Signal Buffer Type Direction
Table 36. Pin Listing by Pin Number
Pin Number Pin Name Signal Buffer Type Direction
C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23
VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC D#[04] VSS D#[07] D#[08] VSS D#[12] LINT0 BPRI# VSS TCK TDO VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS D#[05] D#[13]
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Asynch GTL+ Common Clock Power/Other TAP TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Input/Output Input/Output Input Output Input/Output Input Input Input/Output Input/Output Input/Output
D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
VSS D#[15] D#[23] VSS DEFER# HITM# VSS LINT1 TRST# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC DBI#[0] DSTBN#[0] VSS D#[17] D#[21] VSS RS#[0] VSS HIT# RS#[2] VSS GTLREF TMS VSS VCC VSS
Power/Other Source Synch Source Synch Power/Other Common Clock Common Clock Power/Other Asynch GTL+ TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Power/Other Common Clock Common Clock Power/Other Power/Other TAP Power/Other Power/Other Power/Other Input Input Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input Input Input Input/Output Input/Output Input/Output
Mobile Intel Pentium 4 Processor-M Datasheet
77
Pin Listing and Signal Definitions
Table 36. Pin Listing by Pin Number
Pin Number Pin Name Signal Buffer Type Direction
Table 36. Pin Listing by Pin Number
Pin Number Pin Name Signal Buffer Type Direction
F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G6 G21 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H6 H21 H22 H23 H24 H25
VCC VSS VCC VSS VCC VSS VCC VSS VCC GTLREF DSTBP#[0] VSS D#[19] D#[20] VSS D#[22] ADS# BNR# VSS LOCK# RS#[1] VSS VSS D#[10] D#[18] VSS DBI#[1] D#[25] VSS DRDY# REQ#[4] VSS DBSY# BR0# D#[11] D#[16] VSS D#[26] D#[31]
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Common Clock Common Clock Power/Other Common Clock Common Clock Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Source Synch Power/Other Common Clock Common Clock Source Synch Source Synch Power/Other Source Synch Source Synch Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output
H26 J1 J2 J3 J4 J5 J6 J21 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K6 K21 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L6 L21 L22 L23 L24 L25 L26 M1 M2
VSS REQ#[0] VSS REQ#[3] REQ#[2] VSS TRDY# D#[14] VSS DSTBP#[1] D#[29] VSS DP#[0] A#[06] A#[03] VSS A#[04] REQ#[1] VSS VSS DSTBN#[1] D#[30] VSS DP#[1] DP#[2] VSS A#[09] A#[07] VSS ADSTB#[0] A#[05] D#[24] D#[28] VSS COMP[0] DP#[3] VSS A#[13] VSS
Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Common Clock Common Clock Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Source Synch Power/Other Power/Other Common Clock Power/Other Source Synch Power/Other Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output
78
Mobile Intel Pentium 4 Processor-M Datasheet
Pin Listing and Signal Definitions
Table 36. Pin Listing by Pin Number
Pin Number Pin Name Signal Buffer Type Direction
Table 36. Pin Listing by Pin Number
Pin Number Pin Name Signal Buffer Type Direction
M3 M4 M5 M6 M21 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N6 N21 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P6 P21 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5
A#[10] A#[11] VSS A#[08] D#[27] VSS D#[32] D#[35] VSS D#[37] A#[12] A#[14] VSS A#[15] A#[16] VSS VSS D#[33] D#[36] VSS D#[39] D#[38] COMP[1] VSS A#[19] A#[20] VSS A#[24] D#[34] VSS DSTBP#[2] D#[41] VSS DBI#[2] VSS A#[18] A#[21] VSS ADSTB#[1]
Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch
Input/Output Input/Output
R6 R21 R22
A#[28] D#[40] DSTBN#[2] VSS D#[43] D#[42] VSS A#[17] A#[22] VSS A#[26] A#[30] VSS VSS D#[46] D#[47] VSS D#[45] D#[44] A#[23] VSS A#[25] A#[31] VSS TESTHI8 D#[52] VSS D#[50] D#[49] VSS D#[48] VSS A#[27] A#[32] VSS AP#[1] MCERR# DBI#[3] D#[53]
Source Synch Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Common Clock Source Synch Source Synch
Input/Output Input/Output Input/Output
Input/Output Input/Output
R23 R24 R25
Input/Output Input/Output
Input/Output Input/Output
R26 T1 T2
Input/Output Input/Output
Input/Output Input/Output Input/Output
T3 T4 T5 T6
Input/Output Input/Output
Input/Output Input/Output
T21 T22 T23 T24
Input/Output Input/Output
Input/Output Input/Output
T25 T26 U1
Input/Output Input/Output Input/Output
Input/Output Input/Output Input/Output
U2 U3 U4 U5
Input/Output Input/Output
Input/Output Input/Output
U6 U21 U22
Input Input/Output
Input/Output Input/Output
U23 U24 U25
Input/Output Input/Output
Input/Output Input/Output
U26 V1 V2
Input/Output
Input/Output Input/Output
Input/Output
V3 V4
Input/Output Input/Output
V5 V6 V21
Input/Output Input/Output Input/Output Input/Output
Input/Output
V22
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Table 36. Pin Listing by Pin Number
Pin Number Pin Name Signal Buffer Type Direction
V23 V24 V25 V26 W1 W2 W3 W4 W5 W6 W21 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y21 Y22 Y23 Y24 Y25 Y26
VSS D#[54] D#[51] VSS A#[29] A#[33] VSS TESTHI9 INIT# VSS VSS DSTBN#[3] DSTBP#[3] VSS D#[57] D#[55] A#[34] VSS TESTHI10 STPCLK# VSS BPM#[3] D#[60] VSS D#[58] D#[59] VSS D#[56]
Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Asynch GTL+ Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Power/Other Power/Other Asynch GTL+ Power/Other Common Clock Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output
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5.2
Alphabetical Signals Reference
Table 37. Signal Description (Page 1 of 8)
Name Type Description
A[35:3]#
Input/ Output
A[35:3]# (Address) define a 236-byte physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Mobile Intel Pentium 4 Processor-M system bus. A[35:3]# are protected by parity signals AP[1:0]#. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. On the active-to-inactive transition of RESET#, the processor samples a subset of the A[35:3]# pins to determine power-on configuration. See Section 7.1 for more details. If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/ write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below.
A20M#
Input
ADS#
Input/ Output
ADSTB[1:0]#
Input/ Output
Signals
Associated Strobe
REQ[4:0]#, A[16:3]# A[35:17]#
ADSTB0# ADSTB1#
AP[1:0]#
Input/ Output
AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#, A[35:3]#, and the transaction type on the REQ[4:0]#. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals are high. AP[1:0]# should connect the appropriate pins of all Mobile Intel Pentium 4 Processor-M system bus agents. The following table defines the coverage model of these signals.
Request Signals subphase 1 subphase 2
A[35:24]# A[23:3]# REQ[4:0]#
AP0# AP1# AP1#
AP1# AP0# AP0#
BCLK[1:0]
Input
The differential pair BCLK (Bus Clock) determines the system bus frequency. All processor system bus agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS.
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Pin Listing and Signal Definitions
Table 37. Signal Description (Page 2 of 8)
Name Type Description
BINIT#
Input/ Output
BINIT# (Bus Initialization) may be observed and driven by all processor system bus agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation. If BINIT# observation is enabled during power-on configuration, and BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity and bus request arbitration state machines. The bus agents do not reset their IOQ and transaction tracking state machines upon observation of BINIT# activation. Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for the system bus and attempt completion of their bus queue and IOQ entries. If BINIT# observation is disabled during power-on configuration, a central agent may handle an assertion of BINIT# as appropriate to the error handling architecture of the system. BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins of all Mobile Intel Pentium 4 Processor-M system bus agents. BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness. BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processor. Please refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/ 845MZ Chipset Platform Design Guide. These signals do not have on-die termination and must be terminated on the system board. BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor system bus. It must connect the appropriate pins of all processor system bus agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this pin is sampled to determine the agent ID = 0. This signal does not have on-die termination and must be terminated. BSEL[1:0] (Bus Select) are used to select the processor input clock frequency. Table 5 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. The Mobile Intel Pentium 4 Processor-M operates at a 400 MHz system bus frequency (100 MHz BCLK[1:0] frequency). For more information about these pins, including termination recommendations refer to Section 2.9 and the appropriate platform design guidelines. COMP[1:0] must be terminated on the system board using precision resistors. Refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for details on implementation.
BNR#
Input/ Output
BPM[5:0]#
Input/ Output
BPRI#
Input
BR0#
Input/ Output
BSEL[1:0]
Output
COMP[1:0]
Analog
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Pin Listing and Signal Definitions
Table 37. Signal Description (Page 3 of 8)
Name Type Description
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DBI#.
Quad-Pumped Signal Groups
D[63:0]#
Input/ Output
Data Group
DSTBN#/ DSTBP#
DBI#
D[15:0]# D[31:16]# D[47:32]# D[63:48]#
0 1 2 3
0 1 2 3
Furthermore, the DBI# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is inverted and therefore sampled active high. DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than half of the data bits, within a 16-bit group, would have been asserted electrically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group.
DBI[3:0] Assignment To Data Bus
DBI[3:0]#
Input/ Output
Bus Signal
Data Bus Signals
DBI3# DBI2# DBI1# DBI0#
D[63:48]# D[47:32]# D[31:16]# D[15:0]#
DBR#
Output
DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal. DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on all processor system bus agents. DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of all processor system bus agents. DP[3:0]# (Data parity) provide parity protection for the D[63:0]# signals. They are driven by the agent responsible for driving D[63:0]#, and must connect the appropriate pins of all Mobile Intel Pentium 4 Processor-M system bus agents.
DBSY#
Input/ Output
DEFER#
Input
DP[3:0]#
Input/ Output
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Pin Listing and Signal Definitions
Table 37. Signal Description (Page 4 of 8)
Name Type Description
DPSLP#
Input
DPSLP# when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state. In order to return to the Sleep State, DPSLP# must be deasserted and BCLK[1:0] must be running. DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of all processor system bus agents. Data strobe used to latch in D[63:0]#.
Signals Associated Strobe
DRDY#
Input/ Output
DSTBN[3:0]#
Input/ Output
D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3#
DSTBN0# DSTBN1# DSTBN2# DSTBN3#
Data strobe used to latch in D[63:0]#.
Signals Associated Strobe
DSTBP[3:0]#
Input/ Output
D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3#
DSTBP0# DSTBP1# DSTBP2# DSTBP3#
FERR#/PBE#
Output
FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/ PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/ PBE# is similar to the ERROR# signal on the INTEL 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. For additional information on the pending break event functionality, including the identification of support of the feature and enable/ disable information, refer to volume 3 of the Intel Architecture Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note. The GHI# signal controls the selection of the operating mode bus ratio and voltage in the Mobile Intel Pentium 4 Processor-M. On the Mobile Intel Pentium 4 Processor-M featuring Enhanced Intel SpeedStep technology, this signal is latched on entry to Sleep state and is observed during the Deep Sleep state. GHI# determines which of two performance states is selected for operation. This signal is ignored when the processor is not in the Deep Sleep state. This signal should be driven with an Open-drain driver. Refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for termination and connection guidelines. GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 VCC. GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or logical 1. Refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for more information.
GHI#
Input
GTLREF
Input
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Pin Listing and Signal Definitions
Table 37. Signal Description (Page 5 of 8)
Name Type Description
HIT# HITM#
Input/ Output Input/ Output
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any system bus agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor system bus. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#. This signal does not have on-die termination and must be terminated on the system board. IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins of all processor system bus agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST). ITPCLKOUT[1:0] is an uncompensated differential clock output that is a delayed copy of the BCLK[1:0], which is an input to the processor. This clock output can be used as the differential clock into the ITP port that is designed onto the motherboard. If ITPCLKOUT[1:0] outputs are not used, they must be terminated properly. Refer to Section 2.5 for additional details and termination requirements. ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals. LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of all processor system bus agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the processor system bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock.
IERR#
Output
IGNNE#
Input
INIT#
Input
ITPCLKOUT [1:0]
Output
ITP_CLK[1:0]
Input
LINT[1:0]
Input
LOCK#
Input/ Output
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Table 37. Signal Description (Page 6 of 8)
Name Type Description
MCERR#
Input/ Output
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor system bus agents. MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options: Enabled or disabled. Asserted, if configured, for internal errors along with IERR#. Asserted, if configured, by the request initiator of a bus transaction after it observes an error. Asserted by any bus agent when it observes an error in a bus transaction. For more details regarding machine check architecture, please refer to the IA-32 Software Developer's Manual, Volume 3: System Programming Guide. The assertion of PROCHOT# (Processor Hot) indicates that the processor die temperature has reached its thermal limit. See Section 6 for more details. PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. `Clean' implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. Figure 16 illustrates the relationship of PWRGOOD to the RESET# signal. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width specification in Table 22, and be followed by a 1 to 10 ms RESET# pulse. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. REQ[4:0]# (Request Command) must connect the appropriate pins of all processor system bus agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB0#. Refer to the AP[1:0]# signal description for details on parity checking of these signals. Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications. On observing active RESET#, all system bus agents will deassert their outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while PWRGOOD is asserted. A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These configuration options are described in the Section 7.1. This signal does not have on-die termination and must be terminated on the system board. RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all processor system bus agents. RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins of all processor system bus agents. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this indicates it is not being driven by any agent guaranteeing correct parity.
PROCHOT#
Output
PWRGOOD
Input
REQ[4:0]#
Input/ Output
RESET#
Input
RS[2:0]#
Input
RSP#
Input
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Pin Listing and Signal Definitions
Table 37. Signal Description (Page 7 of 8)
Name Type Description
SKTOCC#
Output
SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers may use this pin to determine if the processor is present. SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will only recognize the assertion of the RESET# signal, deassertion of SLP#, and assertion of DPSLP# input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. If the BCLK input is stopped or if DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and transition to the Deep Sleep state. SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs. Assertion of STPCLK# (Stop Clock) causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the system bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. TESTHI[10:8] and TESTHI[5:0] must be connected to a VCC power source through a resistor for proper processor operation. See Section 2.5 for more details. Thermal Diode Anode. See Section 6. Thermal Diode Cathode. See Section 6.
SLP#
Input
SMI#
Input
STPCLK#
Input
TCK TDI TDO TESTHI[10:8] TESTHI[5:0] THERMDA THERMDC
Input Input Output Input Other Other
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Pin Listing and Signal Definitions
Table 37. Signal Description (Page 8 of 8)
Name Type Description
THERMTRIP#
Output
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond which permanent silicon damage may occur. Measurement of the temperature is accomplished through an internal thermal sensor which is configured to trip at approximately 135C. Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor, its core voltage (Vcc) must be removed following the assertion of THERMTRIP#. See Figure 19 and Table 22 for the appropriate power down sequence and timing requirements. For processors with CPUID of 0xF24: Once activated, THERMTRIP# remains latched until RESET# is asserted. While the assertion of the RESET# signal will de-assert THERMTRIP#, if the processor's junction temperature remains at or above the trip level, THERMTRIP# will again be asserted. For processors with CPUID of 0xF27 or higher: Driving of the THERMTRIP# signal is enabled within 10 us of the assertion of PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated, THERMTRIP# remains latched until PWRGOOD is de-asserted. While the deassertion of the PWRGOOD signal will de-assert THERMTRIP#, if the processor's junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 us of the assertion of PWRGOOD. TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all system bus agents. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. This can be done with a 680 ohm pull-down resistor. VCCA provides isolated power for the internal processor core PLL's. Refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for complete implementation details. VCCIOPLL provides isolated power for internal processor system bus PLL's. Follow the guidelines for VCCA, and refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for complete implementation details. VCCSENSE is an isolated low impedance connection to processor core power (VCC). It can be used to sense or measure power near the silicon with little noise. Independent 1.2-V supply must be routed to VCCVID pin for the Mobile Intel Pentium 4 Processor-M's Voltage Identification circuit. VID[4:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (Vcc). Unlike some previous generations of processors, these are open drain signals that are driven by the Mobile Intel Pentium 4 Processor-M and must be pulled up to 3.3 V (max.) with 1-Kohm resistors. The voltage supply for these pins must be valid before the VR can supply Vcc to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations. See Table 3 for definitions of these pins. The VR must supply the voltage that is requested by the pins, or disable itself. VSSA is the isolated ground for internal PLLs. VSSSENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise.
TMS
Input
TRDY#
Input
TRST#
Input
VCCA
Input
VCCIOPLL
Input
VCCSENSE VCCVID
Output Input
VID[4:0]
Output
VSSA VSSSENSE
Input Output
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Thermal Specifications and Design Considerations
6.
Thermal Specifications and Design Considerations
In order to achieve proper cooling of the processor, a thermal solution (e.g., heat spreader, heat pipe, or other heat transfer system) must make firm contact to the exposed processor die. The processor die must be clean before the thermal solution is attached or the processor may be damaged. Table 38 provides the Thermal Design Power (TDP) dissipation and the minimum and maximum TJ temperatures for the Mobile Intel Pentium 4 Processor-M. A thermal solution should be designed to ensure the junction temperature remains within the minimum and maximum TJ specifications while operating at the Thermal Design Power. Additionally, a secondary failsafe mechanism in hardware would be provided to shutdown the processor under catastrophic thermal conditions, as described in Section 2.4.3. TDP is a thermal design power specification based on the worst case power dissipation of the processor while executing publicly available software under normal operating conditions at nominal voltages. Contact your Intel Field Sales Representative for further information.
Table 38. Power Specifications for the Mobile Intel Pentium 4 Processor-M
Symbol Parameter Min Typ Max Unit Notes
TDP
Thermal Design Power at 2.6 GHz & 1.3 V 2.5 GHz & 1.3 V 2.4 GHz & 1.3 V 2.2 GHz & 1.3 V 2.0 GHz & 1.3 V 1.9 GHz & 1.3 V 1.8 GHz & 1.3 V 1.7 GHz & 1.3 V 1.6 GHz & 1.3 V 1.5 GHz & 1.3 V 1.4 GHz & 1.3 V 1.2 GHz & 1.2 V Auto Halt/Stop Grant/Sleep Power at 1.3 V (for >2.0 GHz) 1.3 V (for <= 2.0 GHz) 1.2 V Deep Sleep Power at 1.3 V 1.2 V Deeper Sleep Power at 1.0 V Junction Temperature 0
35.0 35.0 35.0 35.0 32.0 32.0 30.0 30.0 30.0 26.9 25.8 20.8
W
At 100C, Note 1
PAH PSGNT PSLP
8.0 7.5 5.9 5.0 4.2 2.9 100
W
At 50C, Note 2
PDSLP
W
At 35C, Note 2
PDPRSLP TJ
W C
At 35C, Note 2 Note 3
NOTES: 1. TDP is defined as the worst case power dissipated by the processor while executing publicly available software under normal operating conditions at nominal voltages that meet the load line specifications. The TDP number shown is a specification based on ICC (maximum) at nominal voltages and indirectly tested by this ICC (maximum) testing. TDP definition is synonymous with the Thermal Design Power (typical) specification referred to in the previous EMTS. The Intel TDP specification is a recommended design point
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Thermal Specifications and Design Considerations
and is not representative of the absolute maximum power the processor may dissipate under worst case conditions. 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. The maximum junction temperature (TJ) is specified as the hottest location on the die. The thermal monitor's automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 6.1.1 for TJ measurement guidelines (Refer to Section 6.1.2 for thermal monitor details).
6.1
6.1.1
Thermal Specifications
Thermal Diode
The Mobile Intel Pentium 4 Processor-M incorporates two methods of monitoring die temperature, the thermal monitor and the thermal diode. The thermal monitor (detailed in Section 6.1.2) must be used to determine when the minimum or maximum specified processor junction temperature has been reached. The second method, the thermal diode, can be read by an off-die analog/digital converter (a thermal sensor) located on the motherboard, or a stand-alone measurement kit. The thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but cannot be used to indicate that the maximum TJ of the processor has been reached. Table 39 and Table 40 provide the diode interface and specifications.
Note:
The reading of the thermal sensor connected to the thermal diode does not reflect the temperature of the hottest location on the die (TJ). This is due to inaccuracies in the thermal diode, on-die temperature gradients between the location of the thermal diode and the hottest location on the die, and time based variations in the die temperature. Time based variations can occur since the sampling rate of the sensor is much slower than the die level temperature changes. The offset between the thermal diode based temperature reading and the hottest location of the die (thermal monitor) may be characterized using the thermal monitor's Automatic mode activation of thermal control circuit. This temperature offset must be taken into account when using the processor thermal diode to implement power management events.
Table 39. Thermal Diode Interface
Signal Name Pin/Ball Number Signal Description
THERMDA THERMDC
B3 C4
Thermal diode anode Thermal diode cathode
Table 40. Thermal Diode Specifications
Symbol Parameter Min Typ Max Unit A Notes
IFW n RT
Forward Bias Current Diode Ideality Factor Series Resistance
5 1.0012 1.0021 3.86
300 1.0030
1 2, 3, 4
ohms
2, 3, 5
NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Characterized at 100C. 3. Not 100% tested. Specified by design characterization. 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: IFW=Is *(e(qVD/nkT) -1)
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Thermal Specifications and Design Considerations
Where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). 5. The series resistance, RT, is provided to allow for a more accurate measurement of the diode junction temperature. RT as defined includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. RT can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: Terror = [RT*(N-1)*IFWmin]/[(nk/q)*ln N] Where Terror = sensor temperature error, N = sensor current ration, k = Boltzmann Constant, q = electronic charge.
6.1.2
Thermal Monitor
The thermal monitor feature found in the Mobile Intel Pentium 4 Processor-M allows system designers to design lower cost thermal solutions without compromising system integrity or reliability. By using a factory-tuned, precision on-die thermal sensor, and a fast acting thermal control circuit (TCC), the processor, without the aid of any additional software or hardware, can keep the processor's die temperature within factory specifications under nearly all conditions. The thermal monitor thus allows the processor and system thermal solutions to be designed much closer to the power envelopes of real applications, instead of being designed to the much higher maximum processor power envelopes. The thermal monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks. The processor clocks are modulated when the thermal control circuit (TCC) is activated. The thermal monitor uses two modes to activate the TCC: Automatic mode and OnDemand mode. Automatic mode is required for the processor to operate within specifications and must first be enabled via BIOS. Once automatic mode is enabled, the TCC will activate only when the internal die temperature is very near the temperature limits of the processor. When TCC is enabled, and a high temperature situation exists (i.e. TCC is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30-50%). An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss. Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. Once the temperature has returned to a non-critical level, modulation ceases and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. Processor performance will be decreased by approximately the same amount as the duty cycle when the TCC is active, however, with a properly designed and characterized thermal solution, the TCC will only be activated briefly when running the most power intensive applications in a high ambient temperature environment. For automatic mode, the duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers or interrupt handling routines. The TCC may also be activated via On-Demand mode. If bit 4 of the ACPI Thermal Monitor Control register is written to a 1 the TCC will be activated immediately, independent of the processor temperature. When using On-Demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Thermal Monitor Control register. In automatic mode, the duty cycle is fixed, however in On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. OnDemand mode may be used at the same time Automatic mode is enabled, however, if the system tries to enable the TCC via On-Demand mode at the same time automatic mode is enabled AND a high temperature condition exists, the duty cycle of the automatic mode will override the duty cycle selected by the On-Demand mode.
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Thermal Specifications and Design Considerations
An external signal, PROCHOT# (processor hot) is asserted when the processor die temperature has reached its thermal limit. If the TCC is enabled (note that the TCC must be enabled for the processor to be operating within spec), TCC will be active when the PROCHOT# signal is active. The temperature at which the thermal control circuit activates is not user configurable and is not software visible. Bus snooping and interrupt latching are active while the TCC is active. Besides the thermal sensor and TCC, the thermal monitor feature also includes one ACPI register, performance monitoring logic, bits in three model specific registers (MSR), and one I/O pin (PROCHOT#). All are available to monitor and control the state of the thermal monitor feature. Thermal monitor can be configured to generate an interrupt upon the assertion or de-assertion of PROCHOT#. If automatic mode is disabled the processor will be operating out of specification. Regardless of enabling of the automatic or On-Demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 135 C. At this point the system bus signal THERMTRIP# will go active and stay active until RESET# has been initiated. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. If THERMTRIP# is asserted, processor core voltage (VCC) must be removed within the timeframe defined in Table 22.
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Configuration and Low Power Features
7.
7.1
Configuration and Low Power Features
Power-On Configuration Options
Several configuration options can be configured by hardware. The Mobile Intel Pentium 4 Processor-M samples its hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, please refer to Table 41. Frequency determination functionality will exist on engineering sample processors which means that samples can run at varied frequencies. Production material will have the bus to core ratio locked during manufacturing and can only be operated at the rated frequency. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor.
Table 41. Power-On Configuration Option Pins
Configuration Option Pin1
Output tristate Execute BIST In Order Queue pipelining (set IOQ depth to 1) Disable MCERR# observation Disable BINIT# observation APIC Cluster ID (0-3) Disable bus parking Symmetric agent arbitration ID
SMI# INIT# A7# A9# A10# A[12:11]# A15# BR0#
NOTE: Asserting this signal during RESET# will select the corresponding option.
7.2
Clock Control and Low Power States
The use of AutoHALT, Stop-Grant, Sleep, Deep Sleep and Deeper Sleep states is allowed in Mobile Intel Pentium 4 Processor-M based systems to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 35 for a visual representation of the processor low-power states.
7.2.1
Normal State
This is the normal operating state for the processor.
7.2.2
AutoHALT Powerdown State
AutoHALT is a low-power state entered when the processor executes the HALT instruction. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or PSB interrupt message. RESET# will cause the processor to immediately initialize itself.
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Configuration and Low Power Features
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the AutoHALT Powerdown state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the AutoHALT Powerdown state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in AutoHALT Powerdown state, the processor will process bus snoops.
Figure 35. Clock Control States
STPCLK# asserted Normal STPCLK# de-asserted Stop Grant SLP# de-asserted halt break HLT instruction STPCLK# asserted DPSLP# de-asserted SLP# asserted Sleep
snoop snoop STPCLK# serviced occurs de-asserted snoop occurs
DPSLP# asserted
core voltage raised HALT/ Grant Snoop Deeper Sleep Deep Sleep
Auto Halt
snoop serviced
core voltage lowered
V0001-04
Halt break - A20M#, BINIT#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
7.2.3
Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to VCC) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the system bus should be driven to the inactive state. BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched and can be serviced by software upon exit from the Stop-Grant state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the de-assertion of the STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should only be de-asserted ten or more bus clocks after the deassertion of SLP#. A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the system bus (see Section 7.2.4). A transition to the Sleep state (see Section 7.2.5) will occur with the assertion of the SLP# signal.
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Configuration and Low Power Features
While in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process a system bus snoop.
7.2.4
HALT/Grant Snoop State
The processor will respond to snoop transactions on the system bus while in Stop-Grant state or in AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the system bus has been serviced (whether by the processor or another agent on the system bus). After the snoop is serviced, the processor will return to the Stop-Grant state or AutoHALT Power Down state, as appropriate.
7.2.5
Sleep State
The Sleep state is a low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is in the Stop Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation. Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will cause unpredictable behaviour. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the system bus while the processor is in Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behaviour. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence. While in the Sleep state, the processor is capable of entering an even lower power state, the Deep Sleep state, by asserting the DPSLP# pin. (See Section 7.2.6.) Once in the Sleep or Deep Sleep states, the SLP# pin must be de-asserted if another asynchronous system bus event needs to occur. The SLP# pin has a minimum assertion of one BCLK period. When the processor is in Sleep state, it will not respond to interrupts or snoop transactions.
7.2.6
Deep Sleep State
Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep Sleep state is entered by asserting the DPSLP# pin. The DPSLP# pin must be de-asserted to reenter the Sleep state. A period of 30 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep State. Once in the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state.
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Configuration and Low Power Features
The clock may be stopped when the processor is in the Deep Sleep state in order to support the ACPI S1 state. The clock may only be stopped after DPSLP# is asserted and must be restarted before DPSLP# is deasserted. To provide maximum power conservation when stopping the clock during Deep Sleep, hold the BLCK0 input at VOL and the BCLK1 input at VOH. While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the system bus while the processor is in Deep Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behaviour.
7.2.7
Deeper Sleep State
The Deeper Sleep State is the lowest state power the processor can enter. This state is functionally identical to the Deep Sleep state but at a lower core voltage. The control signals to the voltage regulator to initiate a transition to the Deeper Sleep state are provided on the platform. Please refer the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide.
7.3
Enhanced Intel SpeedStep Technology
The Mobile Intel Pentium 4 Processor-M, when used in conjunction with the requisite Intel SpeedStep technology applet or its equivalent, supports Enhanced Intel SpeedStep technology. Enhanced Intel SpeedStep technology allows the processor to switch between two core frequencies automatically based on CPU demand, without having to reset the processor or change the system bus frequency. The processor has two bus ratios and voltages programmed into it instead of one and the GHI# signal controls which bus ratio and voltage is used. After reset, the processor will start in the lower of its two core frequencies, the "Battery Optimized" mode. An operating mode transition to the high core frequency can be made by setting GHI# low, putting the processor into the Deep Sleep state, regulating to the new VID output, and returning to the Normal state. This puts the processor into the high core frequency, or "Maximum Performance" operating mode. Going through these steps with GHI# set high, transitions the processor back to the low core frequency operating mode. The processor will drive the VID[4:0] pins with the VID of the current operating mode and the system logic is required to regulate the core voltage within specification for the driven VID.
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Debug Tools Specifications
8.
Debug Tools Specifications
Please refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for information regarding debug tools specifications.
8.1
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Mobile Intel Pentium 4 Processor-M systems. Tektronix* and Agilent* should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor. Due to the complexity of Mobile Intel Pentium 4 Processor-M systems, the LAI is critical in providing the ability to probe and capture system bus signals. There are two sets of considerations to keep in mind when designing a Mobile Intel Pentium 4 Processor-M system that can make use of an LAI: mechanical and electrical.
8.1.1
Mechanical Considerations
The LAI is installed between the processor socket and the Mobile Intel Pentium 4 Processor-M. The LAI pins plug into the socket, while the Mobile Intel Pentium 4 Processor-M pins plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the Mobile Intel Pentium 4 Processor-M and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keepout volume remains unobstructed inside the system.
8.1.2
Electrical Considerations
The LAI will also affect the electrical performance of the system bus; therefore, it is critical to obtain electrical load models from each of the logic analyzer vendors to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide.
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